Patents by Inventor Yung-Hui Yeh
Yung-Hui Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130059081Abstract: A method of fabricating a flexible substrate structure is provided. A flexible metal carrier including at least one first region and at least one second region is provided. A surface-modified layer is formed on the first region of the flexible metal carrier. A flexible plastic substrate is formed over the first region and the second region of the flexible metal carrier. The flexible plastic substrate over the first region contacts with the surface-modified layer. The flexible plastic substrate over the second region contacts with the flexible metal carrier.Type: ApplicationFiled: August 31, 2012Publication date: March 7, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yung-Hui Yeh, Chun-Cheng Cheng, Chyi-Ming Leu, Yung-Lung Tseng
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Patent number: 8274035Abstract: A photosensor circuit including a first node, a level shifting circuit, a phototransistor and an inverter is provided. The first node has an operation voltage signal. The level shifting circuit is coupled to the first node for biasing the first node, so that the operation voltage signal is biased to an operation biasing level. The phototransistor is coupled to the first node for receiving an optical signal and accordingly generates a first electrical signal by means of controlling the level of the operation voltage signal. The inverter receives the first electrical signal and accordingly generates and outputs a second electrical signal, which indicates the intensity of the optical signal.Type: GrantFiled: February 25, 2010Date of Patent: September 25, 2012Assignee: Industrial Technology Research InstituteInventors: Shou-En Liu, Yung-Hui Yeh
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Patent number: 8263433Abstract: Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer.Type: GrantFiled: March 18, 2011Date of Patent: September 11, 2012Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
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Patent number: 8257992Abstract: A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern.Type: GrantFiled: March 18, 2011Date of Patent: September 4, 2012Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
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Publication number: 20120171792Abstract: A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern.Type: ApplicationFiled: March 18, 2011Publication date: July 5, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
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Publication number: 20120164766Abstract: Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer.Type: ApplicationFiled: March 18, 2011Publication date: June 28, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yung-Hui Yeh, Chih-Ming Lai, Chun-Cheng Cheng
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Patent number: 8076741Abstract: A photo sensing element array substrate is provided. The photo sensing element array substrate includes a flexible substrate and a plurality of photo sensing elements. The photo sensing elements are disposed in array on the flexible substrate. Each of the photo sensing elements includes a photo sensing thin film transistor (TFT), an oxide semiconductor TFT and a capacitor. The photo sensing TFT is disposed on the flexible substrate. The oxide semiconductor TFT is disposed on the flexible substrate. The oxide semiconductor TFT is electrically connected to the photo sensing TFT. The capacitor is disposed on the flexible substrate and electrically connected between the photo sensing TFT and the oxide semiconductor TFT. When the photo sensing element array substrate is bent, it remains unaffected from normal operation.Type: GrantFiled: April 22, 2009Date of Patent: December 13, 2011Assignee: Industrial Technology Research InstituteInventors: Chih-Ming Lai, Yung-Hui Yeh
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Patent number: 8053836Abstract: An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.Type: GrantFiled: June 1, 2009Date of Patent: November 8, 2011Assignees: Industrial Technology Research Institute, National Taiwan UniversityInventors: Yung-Hui Yeh, Chun-Cheng Cheng, Jian-Jang Huang, Shih-Hua Hsiao, Kuang-Chung Liu
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Patent number: 8039844Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.Type: GrantFiled: August 12, 2008Date of Patent: October 18, 2011Assignee: Industrial Technology Research InstituteInventors: Cheng-Ju Tsai, Bo-Chu Chen, Ding-Kang Shih, Jung-Jie Huang, Yung-Hui Yeh
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Patent number: 7939434Abstract: A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.Type: GrantFiled: May 6, 2008Date of Patent: May 10, 2011Assignee: Industrial Technology Research InstituteInventors: Chih-Yuan Tseng, I Hsuan Peng, Yung-Hui Yeh, Jung-Jie Huang, Cheng-Ju Tsai
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Publication number: 20110073749Abstract: A photosensor circuit including a first node, a level shifting circuit, a phototransistor and an inverter is provided. The first node has an operation voltage signal. The level shifting circuit is coupled to the first node for biasing the first node, so that the operation voltage signal is biased to an operation biasing level. The phototransistor is coupled to the first node for receiving an optical signal and accordingly generates a first electrical signal by means of controlling the level of the operation voltage signal. The inverter receives the first electrical signal and accordingly generates and outputs a second electrical signal, which indicates the intensity of the optical signal.Type: ApplicationFiled: February 25, 2010Publication date: March 31, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shou-En Liu, Yung-Hui Yeh
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Publication number: 20100276682Abstract: An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.Type: ApplicationFiled: June 1, 2009Publication date: November 4, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL TAIWAN UNIVERSITYInventors: Yung-Hui YEH, Chun-Cheng CHENG, Jian-Jang HUANG, Shih-Hua HSIAO, Kuang-Chung LIU
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Publication number: 20100148168Abstract: An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and a first drain. A portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal. The second transistor includes a second gate, a second oxide semiconductor layer, a second source and a second drain. A portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may have different thickness or different carrier concentrations.Type: ApplicationFiled: June 30, 2009Publication date: June 17, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Ming Lai, Chun-Cheng Cheng, Yung-Hui Yeh
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Publication number: 20100127254Abstract: A photo sensing element array substrate is provided. The photo sensing element array substrate includes a flexible substrate and a plurality of photo sensing elements. The photo sensing elements are disposed in array on the flexible substrate. Each of the photo sensing elements includes a photo sensing thin film transistor (TFT), an oxide semiconductor TFT and a capacitor. The photo sensing TFT is disposed on the flexible substrate. The oxide semiconductor TFT is disposed on the flexible substrate. The oxide semiconductor TFT is electrically connected to the photo sensing TFT. The capacitor is disposed on the flexible substrate and electrically connected between the photo sensing TFT and the oxide semiconductor TFT. When the photo sensing element array substrate is bent, it remains unaffected from normal operation.Type: ApplicationFiled: April 22, 2009Publication date: May 27, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-Ming Lai, Yung-Hui Yeh
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Patent number: 7605783Abstract: A driving circuit for a light emitting element, electrically connected to a data line and a scan line and powered by a bias voltage so as to drive the light emitting element, comprising: a first transistor, further comprising: a first gate, electrically connected to the scan line; and a first drain/source, having a first node electrically connected to the data line and a second node; and a second transistor, further comprising: a second gate, electrically connected to the second node of the first drain/source; and a second drain/source, having a first node electrically connected to the bias voltage, and a second node electrically connected to the light emitting element; wherein, an insulation layer and a layer of non-volatile material is formed successively between the semiconductor layer and the second gate of the second transistor.Type: GrantFiled: May 27, 2005Date of Patent: October 20, 2009Assignee: Industrial Technology Research InstituteInventors: Huai-Yuan Tseng, Yung-Hui Yeh
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Patent number: 7599025Abstract: A vertical pixel structure for emi-flective display and a method thereof are provided. The vertical pixel structure has a substrate, a emitting pixel unit arranged on the substrate and a reflective pixel unit arranged on the emitting pixel unit. By using the vertical pixel structure the aperture of the display can be increased, and the power consumption can be reduced as well.Type: GrantFiled: January 2, 2006Date of Patent: October 6, 2009Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Yu-Wu Wang, Yu-Lung Liu, Chi-Chang Liao, Hsing-Lung Wang
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Patent number: 7576736Abstract: A pixel structure for a vertical emissive-reflective (emi-flective) display is provided. The pixel structure has a substrate, a self-light emitting pixel unit arranged on the substrate, and a reflective pixel unit arranged on the self-light emitting pixel unit. By using the vertical pixel structure, the aperture of the display can be increased, and the power consumption can also be decreased.Type: GrantFiled: September 13, 2005Date of Patent: August 18, 2009Assignee: Industrial Technology Research InstituteInventors: Yung-Hui Yeh, Yu-Wu Wang, Chih-Ming Lai, Chi-Chang Liao, Hsing-Lung Wang
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Patent number: 7575966Abstract: A method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel layer of a driving TFT. A first dielectric layer is formed over the substrate. A first opaque metal gate of the switch TFT, a second opaque metal gate of the driving TFT and a scan line are formed on the first dielectric layer. A first source and a first drain of the switch TFT are formed in the first channel layer and a second source and a second drain of the switch TFT are formed in the second channel layer. A patterned transparent metal layer is formed on the first dielectric layer. A data line is formed over the substrate. An OLED is formed over the substrate.Type: GrantFiled: October 20, 2008Date of Patent: August 18, 2009Assignee: Industrial Technology Research InstituteInventors: Chih-Ming Lai, Yung-Hui Yeh, Yi-Hsun Huang
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Publication number: 20090184321Abstract: This invention provides a top-gate microcrystalline thin film transistor and a method for manufacturing the same. An inversion layer channel is formed in a top interface of a microcrystalline active layer, and being separated from an incubation layer in a bottom interface of the microcrystalline active layer. The inversion layer channel is formed in the crystallized layer of the top interface of the microcrystalline active layer. As such, the present microcrystalline thin film transistor has better electrical performance and reliability.Type: ApplicationFiled: August 12, 2008Publication date: July 23, 2009Inventors: Cheng-Ju TSAI, Bo-Chu CHEN, Ding-Kang SHIH, Jung-Jie HUANG, Yung-Hui YEH
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Publication number: 20090179842Abstract: A flat display panel is provided. The flat display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels arranged in an (m×n) array, in which both m and n are integers greater than 2. Each of the pixels includes four sub-pixels arranged in a (2×2) array. In each of the pixels, the sub-pixels are connected with one of the scan lines and one of the data lines correspondingly, and display different color lights, respectively. In any four pixels arranged in a (2×2) array, the four sub-pixels located at the center area display the same color light.Type: ApplicationFiled: September 3, 2008Publication date: July 16, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Bo-Chu Chen, King-Yuan Ho, Yung-Hui Yeh