Patents by Inventor Yusuke Otake

Yusuke Otake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180100486
    Abstract: A wind farm including wind power generation apparatuses the damage degrees of which can be held down and wind power generation apparatuses can be provided without introducing a central processing unit for the wind farm and new wind power generation apparatuses having the rotation directions of their blades different from each other.
    Type: Application
    Filed: August 31, 2017
    Publication date: April 12, 2018
    Inventors: Yusuke OTAKE, Nobuhiro KUSUNO, Hiromu KAKUYA
  • Publication number: 20180097036
    Abstract: A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 5, 2018
    Inventors: Yusuke OTAKE, Toshifumi WAKANO
  • Publication number: 20180090533
    Abstract: A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.
    Type: Application
    Filed: April 13, 2016
    Publication date: March 29, 2018
    Inventors: Yusuke OTAKE, Toshifumi WAKANO
  • Publication number: 20180083062
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 22, 2018
    Applicant: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Publication number: 20180069045
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 8, 2018
    Applicant: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Publication number: 20180027171
    Abstract: The present disclosure relates to an image pickup device that inhibits color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for image plane phase difference AF. The image plane phase difference detection pixel includes: a first photoelectric conversion section; an upper electrode section that is one of electrodes disposed facing each other, the upper electrode section being formed on a light incident side first photoelectric conversion section; and a lower electrode section that is another of the electrodes disposed facing each other, the lower electrode section being formed on an opposite side of the first photoelectric conversion section, the lower electrode section being multiple-divided at a position that avoids a center of the incident light. The present disclosure is applicable to image sensors.
    Type: Application
    Filed: January 29, 2016
    Publication date: January 25, 2018
    Inventors: Kyohei YOSHIMURA, Toshifumi WAKANO, Yusuke OTAKE
  • Patent number: 9865643
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 9, 2018
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Publication number: 20170287972
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Applicant: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Patent number: 9773835
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 26, 2017
    Assignee: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Publication number: 20170236859
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Application
    Filed: August 6, 2015
    Publication date: August 17, 2017
    Inventors: Yusuke OTAKE, Toshifumi WAKANO, Takuya SANO, Yusuke TANAKA, Keiji TATANI, Hideo HARIFUCHI, Eiichi TAUCHI, Hiroki IWASHITA, Akira MATSUMOTO
  • Publication number: 20170110503
    Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Applicant: Sony Corporation
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Tanaka, Yusuke Otake
  • Patent number: 9287423
    Abstract: A solid-state imaging device in which a plurality of pixels are two-dimensionally arranged includes a silicon layer; a plurality of photodiodes which are formed in the silicon layer to correspond to the pixels and generate signal charges by performing photoelectric conversion on incident light; and a plurality of color filters formed above the silicon layer to correspond to the plurality of the pixels. A protrusion is formed in a region on a side of the silicon layer between adjacent ones of the color filters wherein the protrusion has a refractive index lower than refractive indices of the adjacent ones of the color filters and, each of the color filters is in contact with the adjacent ones of the color filters, above the protrusion.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 15, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Mitsuyoshi Mori, Toru Okino, Motonori Ishii, Shigeru Saitou, Yusuke Otake, Kazuo Fujiwara, Yasuhiro Shimada, Yutaka Hirose
  • Patent number: 8698064
    Abstract: A solid-state imaging device according to the present invention includes pixels which are arranged two-dimensionally and each of which includes: a light absorbing layer that converts light into signal charges; a signal read circuit to read out the signal charges, the signal read circuit being formed on a side opposite to a light incident plane side of the light absorbing layer; a metal layer that is formed on the light incident plane side of the light absorbing layer, the metal layer having an aperture to transmit, into the light absorbing layer, light of a wavelength range depending on a shape of the aperture, a driving circuit that applies a voltage to the metal layer to generate, in the light absorbing layer, a potential gradient to collect the signal charges.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Yusuke Otake, Yutaka Hirose, Mitsuyoshi Mori, Toru Okino, Yoshihisa Kato
  • Patent number: 8592874
    Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
  • Patent number: 8471351
    Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
  • Patent number: 8243176
    Abstract: A solid-state image sensor includes: a semiconductor substrate 22; a plurality of pixels 23 arranged on the semiconductor substrate 22 and respectively including photoelectric conversion regions 24; and an isolation region 25 electrically isolating the pixels 23 from one another. The first pixel 31 includes a first photoelectric conversion region 32 and a first color filter 41 having a peak of its optical transmission in a first wavelength range. The second pixel 34 adjacent to the first pixel 31 includes a second photoelectric conversion region 35 and a second color filter 42 having peaks in its optical transmission in the first wavelength range and a second wavelength range including shorter wavelengths than the first wavelength range. A portion 33 of a deep portion of the first photoelectric conversion region 32 extends across the isolation region 25 to reach a portion under the second photoelectric conversion region 35.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: August 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Yusuke Otake, Mitsuyoshi Mori, Shinzou Kouyama, Toru Okino
  • Publication number: 20110291162
    Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.
    Type: Application
    Filed: August 4, 2011
    Publication date: December 1, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Mitsuyoshi MORI, Toru Okino, Yusuke Otake, Kazuo Fujiwara, Hitomi Fujiwara
  • Publication number: 20110284929
    Abstract: In each of pixels 10 arranged in an array pattern, an insulating isolation part 22 electrically isolates adjacent photoelectric conversion elements 11, and the photoelectric conversion element 11 and an amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. A low concentration first isolation diffusion layer 23 is formed below the insulating isolation part 22 constituting the first region A, and a high concentration second isolation diffusion layer 24 and a low concentration first isolation diffusion layer 23 are formed below the insulating isolation part 22 constituting the second region B. A source/drain region of the amplifier transistor 14 in the second region B is formed in a well region 25 formed simultaneously with the second isolation diffusion layer 24.
    Type: Application
    Filed: August 4, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Mitsuyoshi MORI, Kazuo Fujiwara, Toru Okino, Yusuke Otake, Hitomi Fujiwara
  • Publication number: 20100220228
    Abstract: A solid-state image sensor includes: a semiconductor substrate 22; a plurality of pixels 23 arranged on the semiconductor substrate 22 and respectively including photoelectric conversion regions 24; and an isolation region 25 electrically isolating the pixels 23 from one another. The first pixel 31 includes a first photoelectric conversion region 32 and a first color filter 41 having a peak of its optical transmission in a first wavelength range. The second pixel 34 adjacent to the first pixel 31 includes a second photoelectric conversion region 35 and a second color filter 42 having peaks in its optical transmission in the first wavelength range and a second wavelength range including shorter wavelengths than the first wavelength range. A portion 33 of a deep portion of the first photoelectric conversion region 32 extends across the isolation region 25 to reach a portion under the second photoelectric conversion region 35.
    Type: Application
    Filed: June 2, 2009
    Publication date: September 2, 2010
    Inventors: Yusuke Otake, Mitsuyoshi Mori, Shinzou Kouyama, Toru Okino