Patents by Inventor Yusuke Otake

Yusuke Otake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11626432
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 11, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
  • Publication number: 20230038698
    Abstract: The present technique relates to an imaging element and a distance measurement module capable of reducing parasitic capacity._A distance measurement module includes: a first wiring that connects predetermined transistors in first adjacent pixels to a via formed in one of first adjacent pixels and connected to a wiring formed in another layer; and a second wiring that connects predetermined transistors in second adjacent pixels to a via formed in a pixel that is adjacent to one of second adjacent pixels and connected to a wiring formed in another layer, in which the first wiring is connected to a redundant wiring. The present technique can be applied to a distance measurement sensor that performs distance measurement, for example.
    Type: Application
    Filed: January 18, 2021
    Publication date: February 9, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hideki ARAI, Yusuke OTAKE, Takuro MURASE, Takeshi YAMAZAKI
  • Publication number: 20230040457
    Abstract: A photodetector including: an amplification region that includes a PN junction provided in a depth direction in a semiconductor layer and that is to be electrically coupled to a cathode; a separation region that defines a pixel region including the amplification region; a hole accumulation region that is provided along a side surface of the separation region and that is to be electrically coupled to an anode; and a gate electrode provided in a region between the amplification region and the hole accumulation region and stacked over the semiconductor layer with a gate insulating film interposed therebetween.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 9, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Katsuhisa TANAKA, Yusuke OTAKE
  • Publication number: 20220397651
    Abstract: Disclosed herein is a ranging module including a light receiving element, a light emitting unit, and a light-emission control unit. The light receiving element has plural transfer gates which distribute and transfer, to plural floating diffusions, signal charge accumulated in a photodiode that photoelectrically converts incident light, and at least two of the plural transfer gates are disposed point-symmetrically with respect to an optical center as seen from a direction of incidence of the light. The light emitting unit emits irradiation light having a periodically varying brightness. The light-emission control unit controls irradiation timing of the irradiation light.
    Type: Application
    Filed: November 19, 2020
    Publication date: December 15, 2022
    Inventors: Takuro Murase, Yusuke Otake, Toshifumi Wakano
  • Patent number: 11523078
    Abstract: Provided is a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. The solid-state imaging device includes a first pixel separation region that separates a plurality of unit pixels including two or more subpixels, a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 6, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi Yamashita, Shohei Shimada, Yusuke Otake, Yusuke Tanaka, Toshifumi Wakano
  • Publication number: 20220291347
    Abstract: An imaging element includes a photoelectric converting section configured to perform photoelectric conversion, a plurality of charge storage sections configured to store charge obtained by the photoelectric converting section, and a plurality of transfer sections configured to transfer the charge from the photoelectric converting section to each of the plurality of charge storage sections. Each of the charge storage sections is provided between a first gate of a transistor included in a corresponding one of the transfer sections and a second gate provided at a position parallel to the first gate.
    Type: Application
    Filed: August 7, 2020
    Publication date: September 15, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Toshifumi WAKANO
  • Publication number: 20220272270
    Abstract: The present disclosure relates to an image pickup device that enables inhibition of occurrence of color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for obtaining a phase difference signal for image plane phase difference AF.
    Type: Application
    Filed: May 12, 2022
    Publication date: August 25, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kyohei YOSHIMURA, Toshifumi WAKANO, Yusuke OTAKE
  • Patent number: 11411034
    Abstract: A solid-state imaging device according to the present disclosure includes a photoelectric conversion film that is provided outside a semiconductor substrate on a pixel-by-pixel basis, performs photoelectric conversion on light having a predetermined wavelength range, and transmits light having wavelength ranges other than the predetermined wavelength range, and a photoelectric conversion region that is provided inside the semiconductor substrate on a pixel-by-pixel basis and performs photoelectric conversion on the light having the wavelength ranges, the light having the wavelength ranges having passed through the photoelectric conversion film. The photoelectric conversion film includes a film having an avalanche function.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 9, 2022
    Assignee: SONY CORPORATION
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Otake
  • Patent number: 11411032
    Abstract: An imaging device comprises a sensor substrate including a pixel array that includes at least a first pixel. The first pixel includes an avalanche photodiode including a light receiving region, a cathode, and an anode. The first pixel includes a wiring layer electrically connected to the cathode and arranged in the sensor substrate such that the wiring layer is in a path of incident light that exits the light receiving region.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 9, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Akira Tanaka, Yusuke Otake, Toshifumi Wakano
  • Patent number: 11404595
    Abstract: An avalanche photodiode (APD) sensor includes a photoelectric conversion region disposed in a substrate and that converts light incident to a first side of the substrate into electric charge, and a cathode region disposed at a second side of the substrate. The second side is opposite the first side. The APD sensor includes an anode region disposed at the second side of the substrate, a first region of a first conductivity type disposed in the substrate, and a second region of a second conductivity type disposed in the substrate. The second conductivity type is different than the first conductivity type. In a cross-sectional view, the first region and the second region are between the photoelectric conversion region and the second side of the substrate. In the cross-sectional view, an interface between the first region and the second region has an uneven pattern.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 2, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshifumi Wakano, Yusuke Otake
  • Patent number: 11363186
    Abstract: The present disclosure relates to an image pickup device that enables inhibition of occurrence of color mixture or noise, and an electronic apparatus. The image pickup device of the present disclosure includes an image plane phase difference detection pixel for obtaining a phase difference signal for image plane phase difference AF.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 14, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kyohei Yoshimura, Toshifumi Wakano, Yusuke Otake
  • Publication number: 20220181366
    Abstract: A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 9, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro YAGI, Yusuke OTAKE, Kyosuke ITO
  • Publication number: 20220181374
    Abstract: A sensor chip according to an embodiment of the present disclosure includes: a photoelectric conversion section including a multiplication region that avalanche-multiplies carriers by a high electric field region; a light-condensing section that condenses incident light toward the photoelectric conversion section; and a pixel array in which a plurality of pixels each including the photoelectric conversion section and the light-condensing section are arranged in array and at least one of a structure of the photoelectric conversion section or a structure of the light-condensing section is changed stepwise from a middle part toward an outer peripheral part.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 9, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kyosuke ITO, Toshifumi WAKANO, Yusuke OTAKE
  • Patent number: 11333549
    Abstract: An avalanche photodiode sensor includes a photoelectric conversion region disposed in a substrate and that converts incident light into electric charge. The avalanche photodiode sensor includes a first region of a first conductivity type on the photoelectric conversion region, and a cathode disposed in the substrate adjacent to the first region and coupled to the photoelectric conversion region. The avalanche photodiode sensor includes an anode disposed in the substrate adjacent to the cathode, and a contact of the first conductivity type disposed in the substrate. An impurity concentration of the first region is different than an impurity concentration of the contact.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: May 17, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kyosuke Ito, Toshifumi Wakano, Yusuke Otake
  • Publication number: 20220149090
    Abstract: The present technology relates to a light detecting element and a method of manufacturing the same that make it possible to reduce pixel size. The light detecting element includes a plurality of pixels arranged in the form of a matrix. Each of the pixels includes a first semiconductor layer of a first conductivity type formed in an outer peripheral portion in the vicinity of a pixel boundary, and a second semiconductor layer of a second conductivity type opposite from the first conductivity type formed on the inside of the first semiconductor layer as viewed in plan. A high field region formed by the first semiconductor layer and the second semiconductor layer when a reverse bias voltage is applied is configured to be formed in a depth direction of a substrate. The present technology is, for example, applicable to a photon counter or the like.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 12, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Toshifumi WAKANO
  • Publication number: 20220077218
    Abstract: An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenji KOBAYASHI, Toshifumi WAKANO, Yusuke OTAKE
  • Patent number: 11264420
    Abstract: The present technology relates to a light detecting element and a method of manufacturing the same that make it possible to reduce pixel size. The light detecting element includes a plurality of pixels arranged in the form of a matrix. Each of the pixels includes a first semiconductor layer of a first conductivity type formed in an outer peripheral portion in the vicinity of a pixel boundary, and a second semiconductor layer of a second conductivity type opposite from the first conductivity type formed on the inside of the first semiconductor layer as viewed in plan. A high field region formed by the first semiconductor layer and the second semiconductor layer when a reverse bias voltage is applied is configured to be formed in a depth direction of a substrate. The present technology is, for example, applicable to a photon counter or the like.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: March 1, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano
  • Publication number: 20220020789
    Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke OTAKE, Akira MATSUMOTO, Junpei YAMAMOTO, Ryusei NAITO, Masahiko NAKAMIZO, Toshifumi WAKANO
  • Patent number: 11222916
    Abstract: An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 11, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kenji Kobayashi, Toshifumi Wakano, Yusuke Otake
  • Publication number: 20210343777
    Abstract: The present disclosure relates to a solid-state imaging element and an electronic device capable of increasing the capacitance of a charge holding unit. The solid-state imaging element includes a pixel including a photodiode, an FD that accumulates charges generated in the photodiode, and a charge holding unit that is connected in parallel with the FD. The charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential. The present disclosure can be applied to a solid-state imaging element that performs global shutter type imaging.
    Type: Application
    Filed: September 5, 2019
    Publication date: November 4, 2021
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke OTAKE, Toshifumi WAKANO, Takuro MURASE