Patents by Inventor Yutaka Shinagawa
Yutaka Shinagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7286410Abstract: A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area to store information in accordance with a variable threshold voltage. At least one condition of the following conditions of the first nonvolatile memory area is made different from that of the second nonvolatile memory area: erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area.Type: GrantFiled: August 3, 2005Date of Patent: October 23, 2007Assignee: Renesas Technology Corp.Inventors: Hiroyuki Tanikawa, Toshihiro Tanaka, Yutaka Shinagawa, Takashi Yamaki
-
Publication number: 20070153618Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: ApplicationFiled: March 2, 2007Publication date: July 5, 2007Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
-
Patent number: 7190615Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: GrantFiled: March 29, 2004Date of Patent: March 13, 2007Assignee: Renesas Technology Corp.Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
-
Publication number: 20060239072Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.Type: ApplicationFiled: June 23, 2006Publication date: October 26, 2006Inventors: Toshihiro Tanaka, Takashi Yamaki, Yutaka Shinagawa, Daisuke Okada, Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru
-
Publication number: 20060220100Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: May 2, 2006Publication date: October 5, 2006Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
-
Patent number: 7085157Abstract: A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.Type: GrantFiled: March 22, 2004Date of Patent: August 1, 2006Assignee: Renesas Technology Corp.Inventors: Toshihiro Tanaka, Takashi Yamaki, Yutaka Shinagawa, Daisuke Okada, Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru
-
Patent number: 7072218Abstract: A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver has in a current path of the high voltages, a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is switched to an off-state first and the other transistor is switched to an on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already shut off, and therefore the high voltage output driver does not break down.Type: GrantFiled: July 3, 2002Date of Patent: July 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masamichi Fujito, Yuko Nakamura, Kazufumi Suzukawa, Toshihiro Tanaka, Yutaka Shinagawa
-
Publication number: 20060123299Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.Type: ApplicationFiled: January 11, 2006Publication date: June 8, 2006Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
-
Patent number: 7057230Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: GrantFiled: July 22, 2002Date of Patent: June 6, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
-
Publication number: 20060044871Abstract: The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies.Type: ApplicationFiled: August 3, 2005Publication date: March 2, 2006Inventors: Hiroyuki Tanikawa, Toshihiro Tanaka, Yutaka Shinagawa, Takashi Yamaki
-
Patent number: 7000160Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.Type: GrantFiled: February 27, 2002Date of Patent: February 14, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
-
Publication number: 20050265114Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: ApplicationFiled: August 5, 2005Publication date: December 1, 2005Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
-
Publication number: 20050258474Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.Type: ApplicationFiled: July 22, 2002Publication date: November 24, 2005Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
-
Patent number: 6963507Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: April 21, 2003Date of Patent: November 8, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
-
Patent number: 6842376Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: August 12, 2003Date of Patent: January 11, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
-
Publication number: 20040212014Abstract: There are included a high voltage output driver (1) which derives operational power from high voltages and a switching circuit (2) which reverses the output state of the high voltage output driver. The high voltage output driver includes on a current path of the high voltages a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is turned to the off-state first and another transistor is turned to the on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already cut off, and therefore the high voltage output driver does not break down.Type: ApplicationFiled: February 12, 2004Publication date: October 28, 2004Inventors: Masamichi Fujito, Yuko Nakamura, Kazufumi Suzukawa, Toshihiro Tanaka, Yutaka Shinagawa
-
Publication number: 20040202020Abstract: The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.Type: ApplicationFiled: March 29, 2004Publication date: October 14, 2004Applicant: Renesas Technology Corp.Inventors: Masamichi Fujito, Yutaka Shinagawa, Kazufumi Suzukawa, Ayako Kakuda, Akira Kato, Toshihiro Tanaka
-
Publication number: 20040196695Abstract: Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.Type: ApplicationFiled: March 22, 2004Publication date: October 7, 2004Applicant: Renesas Technology Corp.Inventors: Toshihiro Tanaka, Takashi Yamaki, Yutaka Shinagawa, Daisuke Okada, Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru
-
Patent number: 6747895Abstract: This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC0 among flash memory cells MC0 to MC2 formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL0 in which the memory cell MC0 is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL0. As a result, parasitic capacitances Ca1 and Ca2 generated between p type wells PWL1 and PWL2 in which the unselected memory cells MC1 and MC2 are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units.Type: GrantFiled: February 27, 2002Date of Patent: June 8, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yukiko Umemoto, Toshihiro Tanaka, Hiroyuki Tanikawa, Yutaka Shinagawa
-
Patent number: 6711061Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: August 20, 2002Date of Patent: March 23, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa