Patents by Inventor Yutaka Shinagawa
Yutaka Shinagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040047223Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: August 12, 2003Publication date: March 11, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20030206451Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “1” (or logic “1) is successively performed.Type: ApplicationFiled: April 21, 2003Publication date: November 6, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Patent number: 6643193Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.Type: GrantFiled: September 20, 2002Date of Patent: November 4, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Yamaki, Kan Takeuchi, Mitsuru Hirakii, Toshihiro Tanaka, Yutaka Shinagawa, Masamichi Fujito
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Patent number: 6567313Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: GrantFiled: September 28, 2001Date of Patent: May 20, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Patent number: 6542411Abstract: A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.Type: GrantFiled: October 5, 2001Date of Patent: April 1, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyuki Tanikawa, Toshihiro Tanaka, Yutaka Shinagawa, Yoshiki Kawajiri, Masamichi Fujito
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Patent number: 6519184Abstract: In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three stages or more in a direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete the write or erase in a short time.Type: GrantFiled: February 26, 2002Date of Patent: February 11, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Toshihiro Tanaka, Hiroyuki Tanikawa, Masayoshi Nakano, Norio Oza, Koki Watanabe, Yutaka Shinagawa
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Publication number: 20030016566Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.Type: ApplicationFiled: September 20, 2002Publication date: January 23, 2003Applicant: Hitachi, Ltd.Inventors: Takashi Yamaki, Kan Takeuchi, Mitsuru Hiraki, Toshihiro Tanaka, Yutaka Shinagawa, Masamichi Fujito
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Publication number: 20030012052Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: August 20, 2002Publication date: January 16, 2003Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Patent number: 6480418Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.Type: GrantFiled: September 14, 2001Date of Patent: November 12, 2002Assignee: Hitachi, Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara
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Patent number: 6477090Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.Type: GrantFiled: August 28, 2001Date of Patent: November 5, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Yamaki, Kan Takeuchi, Mitsuru Hiraki, Toshihiro Tanaka, Yutaka Shinagawa, Masamichi Fujito
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Publication number: 20020159291Abstract: This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC0 among flash memory cells MC0 to MC2 formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL0 in which the memory cell MC0 is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL0. As a result, parasitic capacitances Ca1and Ca2 generated between p type wells PWL1 and PWL2 in which the unselected memory cells MC1 and MC2 are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units.Type: ApplicationFiled: February 27, 2002Publication date: October 31, 2002Applicant: Hitachi, Ltd.Inventors: Yukiko Umemoto, Toshihiro Tanaka, Hiroyuki Tanikawa, Yutaka Shinagawa
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Publication number: 20020153917Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.Type: ApplicationFiled: February 27, 2002Publication date: October 24, 2002Applicant: Hitachi, Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
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Publication number: 20020154545Abstract: In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three stages or more in a direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete the write or erase in a short time.Type: ApplicationFiled: February 26, 2002Publication date: October 24, 2002Applicant: Hitachi, Ltd.Inventors: Toshihiro Tanaka, Hiroyuki Tanikawa, Masayoshi Nakano, Norio Oza, Koki Watanabe, Yutaka Shinagawa
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Patent number: 6459619Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: GrantFiled: November 7, 2001Date of Patent: October 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20020054510Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.Type: ApplicationFiled: November 7, 2001Publication date: May 9, 2002Inventors: Nozomu Matsuzaki, Kazuyoshi Shiba, Yasuhiro Taniguchi, Toshihiro Tanaka, Yutaka Shinagawa
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Publication number: 20020048193Abstract: The invention includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.Type: ApplicationFiled: October 5, 2001Publication date: April 25, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Tanikawa, Toshihiro Tanaka, Yutaka Shinagawa, Yoshiki Kawajiri, Masamichi Fujito
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Publication number: 20020041527Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.Type: ApplicationFiled: September 28, 2001Publication date: April 11, 2002Applicant: Hitachi, Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazufumi Suzukawa, Masamichi Fujito, Takashi Yamaki, Kiichi Makuta, Masashi Wada, Yoshiki Kawajiri
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Publication number: 20020027233Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.Type: ApplicationFiled: August 28, 2001Publication date: March 7, 2002Applicant: Hitachi, Ltd.Inventors: Takashi Yamaki, Kan Takeuchi, Mitsuru Hirakii, Toshihiro Tanaka, Yutaka Shinagawa, Masamichi Fujito
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Publication number: 20020008992Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.Type: ApplicationFiled: September 14, 2001Publication date: January 24, 2002Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara
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Patent number: 6307780Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.Type: GrantFiled: July 27, 2000Date of Patent: October 23, 2001Assignee: Hitachi, Ltd.Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara