Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

Abstract: In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed.

Abstract: In a semiconductor integrated circuit device, such as a ROM having an instruction program set therein, in which an order for selecting word lines is variously different depending upon written information; a method of manufacture which can shorten a production process after the determination of the instruction program or the circuit arrangement of a decoder without adding to a manufacturing step is disclosed.

Abstract: A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.

Abstract: A semiconductor memory includes a word line driving circuit whose output terminal is coupled to one end of each word line of a memory array, and also an auxiliary driving circuit which drives the other end of the word line upon receiving a selection signal transmitted to the other end of this word line. The auxiliary driving circuit comprises a level detector circuit which is dynamically driven by a timing signal, and a driving element which is driven by an output of the level detector circuit to drive the other end of the word line. When the word line is to be reset, the output of the level detector circuit is set at a level which brings the driving element into an "off" state. The auxiliary driving circuit of this arrangement permits the other end of the word line to change to a selection level quickly and to be reset quickly.