Patents by Inventor Yutaka Shionoiri

Yutaka Shionoiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9123581
    Abstract: An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Yutaka Shionoiri, Kiyoshi Kato
  • Patent number: 9117701
    Abstract: Noise generated on a word line is reduced without increasing a load on the word line. A semiconductor device is provided in which a plurality of storage elements each including at least one switching element are provided in matrix; each of the plurality of storage elements is electrically connected to a word line and a bit line; the word line is connected to a gate (or a source and a drain) of a transistor in which minority carriers do not exist substantially; and capacitance of the transistor in which minority carriers do not exist substantially can be controlled by controlling a potential of a source and a drain (or a gate) the transistor in which minority carriers do not exist substantially. The transistor in which minority carriers do not exist substantially may include a wide band gap semiconductor.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 25, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Tomatsu, Hidetomo Kobayashi, Yutaka Shionoiri
  • Patent number: 9114718
    Abstract: An object is to provide a moving object structure capable of reducing power loss caused when power is supplied from a power feeding device to a moving object by wireless communication. Another object is to provide a moving object structure capable of reducing the strength of a radio wave radiated to the surroundings. Before power is supplied to a moving object, a radio wave for alignment of antennas is output from a power feeding device. That is, radio waves are output from a power feeding device in two stages. In a first stage, a radio wave is output to align positions of antennas of the power feeding device and the moving object. In a second stage, a radio wave is output to supply power from the power feeding device to the moving object.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: August 25, 2015
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., INC.
    Inventors: Shunpei Yamazaki, Jun Koyama, Yutaka Shionoiri
  • Patent number: 9117415
    Abstract: A display device comprises a display panel composed of a pixel portion in which a plurality of TFTs are arranged in matrix, a source driver, and a gate driver, an image signal processing circuit for processing an image signal input from an external, and a control circuit for controlling the display panel and the image signal processing circuit. The image signal processing circuit corrects the image signal on the basis of a correction table. By feeding the display panel with the corrected image signal, the display device can provide a good quality image.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: August 25, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masaaki Hiroki, Munehiro Azami, Mitsuaki Osame, Yutaka Shionoiri, Shou Nagao
  • Patent number: 9111795
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Publication number: 20150214378
    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 30, 2015
    Inventors: Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shuhei Nagatsuka, Yutaka Shionoiri
  • Patent number: 9088269
    Abstract: A semiconductor device having a power-saving circuit. The semiconductor device includes an input-output terminal and a holding circuit. When the input-output terminal is used, an inverter loop of the holding circuit is made not to operate by controlling a switch, and when the input-output terminal is not used, the inverter loop of the holding circuit operate by controlling the switch. Power consumption of the holding circuit can be reduced. An OS transistor is preferably used for the switch.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Yuto Yakubo
  • Patent number: 9088245
    Abstract: An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Yutaka Shionoiri
  • Patent number: 9087280
    Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Jun Koyama, Yutaka Shionoiri
  • Publication number: 20150188435
    Abstract: One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.
    Type: Application
    Filed: March 11, 2015
    Publication date: July 2, 2015
    Inventors: Yutaka SHIONOIRI, Junpei SUGAO
  • Patent number: 9057758
    Abstract: An object is to provide a current measurement method which enables a minute current to be measured. To achieve this, the value of a current flowing through an electrical element is not directly measured, but is calculated from a change in potential observed in a predetermined period. The detection of a minute current can be achieved by a measurement method including the steps of applying a predetermined potential to a first terminal of an electrical element comprising the first terminal and a second terminal; measuring an amount of change in potential of a node connected to the second terminal; and calculating, from the amount of change in potential, a value of a current flowing between the first terminal and the second terminal of the electrical element.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Yusuke Sekine, Yutaka Shionoiri
  • Patent number: 9057920
    Abstract: An object of the present invention is to provide a transflective liquid crystal display device having an excellent visibility obtained by optimizing the arrangement of a color filter, which would become a problem in the process of fabricating transparent and reflective liquid crystal display devices, for the transflective liquid crystal display device. In the present invention, the arrangement of a color filter is optimized for improving the visibility of the transflective liquid crystal display device. In addition, the structure, which allows the formation of color filters without increasing the capacitance that affects on a display, is fabricated. Furthermore, in the process of fabricating the transflective liquid crystal display device, an uneven structure is additionally formed without particularly increasing an additional patterning step for the formation of such an uneven structure.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yutaka Shionoiri
  • Patent number: 9059704
    Abstract: An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Jun Koyama, Yutaka Shionoiri, Masami Endo, Hiroki Dembo, Tatsuji Nishijima, Hidetomo Kobayashi, Kazuaki Ohshima
  • Publication number: 20150129873
    Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 14, 2015
    Inventors: Masashi FUJITA, Yutaka SHIONOIRI, Hiroyuki TOMATSU, Hidetomo KOBAYASHI
  • Publication number: 20150108470
    Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor, A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 23, 2015
    Inventors: Shunpei Yamazaki, Shuhei Nagatsuka, Tatsuya Onuki, Yutaka Shionoiri, Kiyoshi Kato, Hidekazu Miyairi
  • Publication number: 20150091629
    Abstract: A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 2, 2015
    Inventors: Takahiko ISHIZU, Kiyoshi KATO, Yutaka SHIONOIRI, Tatsuya ONUKI
  • Patent number: 8994430
    Abstract: To reduce power consumption of a circuit (TEDC) which detects timing errors in a main flip-flop by determining whether or not output data signals of the main flip-flop and a shadow flip-flop correspond. The TEDC includes a power gating circuit (PGC) which performs power gating of the shadow FF and a reset circuit (RSTC) which resets an output signal of the shadow FF. The PGC makes the shadow FF in an active mode only when error detection needs to be performed; other than that, the PGC makes the shadow FF in a power saving mode. The RSTC supplies a certain voltage to an output terminal of the shadow FF in the power saving mode to suppress malfunction of the TEDC. A transistor using an oxide semiconductor is used to supply the voltage to the output terminal.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Patent number: 8982589
    Abstract: One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Junpei Sugao
  • Publication number: 20150048376
    Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
    Type: Application
    Filed: August 29, 2014
    Publication date: February 19, 2015
    Inventors: Hajime Kimura, Yutaka Shionoiri
  • Patent number: 8952728
    Abstract: An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiya Takewaki, Yutaka Shionoiri, Koichiro Kamata