Patents by Inventor Yutaka Shionoiri

Yutaka Shionoiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130308372
    Abstract: A storage device in which held voltage is prevented from decreasing due to feedthrough in writing data to the storage device at high voltage is provided. The storage device includes a write circuit, a bit line, a word line, a transistor, and a capacitor. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor. The other terminal of the capacitor is electrically connected to a ground. The write circuit includes an element holding write voltage and a circuit gradually decreasing voltage from the element holding write voltage. The write voltage is output from the write circuit to the word line.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 21, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Seiko Inoue
  • Patent number: 8581631
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: November 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8575960
    Abstract: A programmable analog device in which data can be held even when supply of a power supply potential is stopped. The programmable circuit includes unit cells connected in parallel or in series, and each of the unit cells includes an analog element. A conduction state of each of the unit cells is changed between an on state and an off state. Each of the unit cells includes, as a switch of the unit cell, a first transistor having a sufficiently low off-state current and a second transistor, a gate electrode of the second transistor being electrically connected to a source or drain electrode of the first transistor. The conduction state of the unit cell is controlled with a potential of the gate electrode of the second transistor, which can be kept even when no power is supplied thanks to the low off-state current of the first transistor.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Ohmaru, Yutaka Shionoiri
  • Publication number: 20130285464
    Abstract: To provide a power feeding system and the like with which charging can be performed without a decrease in the power supply efficiency. To provide a power feeding system and the like with which can offer a power feeding service which is efficient to both a power feeding user and a power feeding provider. The power transmission state in each of power transmitting portions is monitored, the power transmitting portion having the highest power transmission efficiency is selected based on positional advantage, and the power transmitting resonance coil included in the selected power transmitting portion is kept at a first resonance frequency, whereby power transmission continues. The resonance frequency of the power transmitting resonance coil included in the non-selected power transmitting portion (the number of the non-selected power transmitting portions may be plural) is set to a second resonance frequency, whereby power transmission is stopped.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 31, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY., LTD.
    Inventors: Misako Miwa, Koichiro Kamata, Yutaka Shionoiri, Shuhei Maeda
  • Publication number: 20130290747
    Abstract: Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 31, 2013
    Inventors: Misako MIWA, Yutaka SHIONOIRI
  • Patent number: 8570065
    Abstract: A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Masami Endo, Yutaka Shionoiri, Hiroki Dembo, Tatsuji Nishijima, Kazuaki Ohshima, Seiichi Yoneda, Jun Koyama
  • Patent number: 8570070
    Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
  • Publication number: 20130264574
    Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Hajime Kimura, Yutaka Shionoiri
  • Patent number: 8552712
    Abstract: One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Yusuke Sekine, Yutaka Shionoiri, Kazuma Furutani
  • Publication number: 20130251091
    Abstract: A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node ? is raised. When the potential of the node ? reaches (VDD?VthN), the node ? becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105.
    Type: Application
    Filed: February 6, 2013
    Publication date: September 26, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shou Nagao, Yoshifumi Tanada, Yutaka Shionoiri, Hiroyuki Miyake
  • Patent number: 8540161
    Abstract: An object of this invention is to provide a semiconductor device (an RFID) with reduced loss of voltage/current corresponding to a threshold value of a transistor, and having a voltage/current rectification property. Another object of this invention is to simplify a fabrication process and a circuit configuration. A rectifier circuit is provided in an element included in a semiconductor device (RFID) capable of communicating data wirelessly. As compared to the case where only a diode is provided, coils are provided between gate terminals and drain terminals of transistors constituting the diode in a rectifier circuit, so that the coils overlap an antenna which receives a radio wave, whereby a voltage output by the rectifier circuit is increased using electromagnetic coupling between the antenna which receives a radio wave and the coils, so that the rectification efficiency is improved.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 24, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Tatsuji Nishijima, Misako Sato, Shuhei Maeda
  • Patent number: 8525585
    Abstract: An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Yutaka Shionoiri
  • Patent number: 8456402
    Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yutaka Shionoiri
  • Patent number: 8441099
    Abstract: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Publication number: 20130002326
    Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
    Type: Application
    Filed: June 22, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
  • Patent number: 8330498
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8331873
    Abstract: In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Publication number: 20120311365
    Abstract: An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
    Type: Application
    Filed: May 22, 2012
    Publication date: December 6, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Seiichi Yoneda, Jun Koyama, Yutaka Shionoiri, Masami Endo, Hiroki Dembo, Tatsuji Nishijima, Hidetomo Kobayashi, Kazuaki Ohshima
  • Publication number: 20120294067
    Abstract: In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to be wrong. Note that the arithmetic portion controls transmission and reception of the instruction between the flip-flop and the memory which are included in the reading portion. This enables elimination of redundant operations in the reading portion in the case where an instruction read by the reading portion after the branch prediction turns out to be wrong is a subroutine, or the like. That is, the instruction held in the memory is transmitted back to the flip-flop without rereading of the same instruction by the reading portion, whereby the instruction can be output to the arithmetic portion.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidetomo KOBAYASHI, Yutaka SHIONOIRI, Tatsuji NISHIJIMA
  • Publication number: 20120292613
    Abstract: The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yutaka SHIONOIRI, Hidetomo KOBAYASHI