Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a nanostructured layer on a substrate, forming a gate structure surrounding the nanostructured layer, forming a S/D region adjacent to the nanostructured layer, forming a contact opening on the S/D region, depositing a first conductive layer in the contact opening using a first deposition process, performing a plasma etch process on the first conductive layer, depositing a second conductive layer on the first conductive layer using a second deposition process different from the first deposition process, and depositing a metal layer on the second conductive layer.

Abstract: A semiconductor structure includes: a substrate including a plurality of fin structures; a dielectric layer, disposed over adjacent fin structures, wherein a top surface of the dielectric layer is a substantially planar surface; a bit line structure, disposed over the substrate and between adjacent fin structures, wherein the bit line structure includes a polysilicon layer contacting the top surface of the dielectric layer; and a spacer structure, surrounding the bit line structure, wherein the spacer structure contacts the top surface of the dielectric layer. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor structure includes: a substrate, including a plurality of fin structures; a dielectric layer, disposed over adjacent fin structures, wherein a top surface of the dielectric layer is a substantially planar surface; a bit line structure, disposed over the substrate and between adjacent fin structures, wherein the bit line structure includes a polysilicon layer contacting the top surface of the dielectric layer; and a spacer structure, surrounding the bit line structure, wherein the spacer structure contacts the top surface of the dielectric layer. A method of manufacturing the semiconductor structure is also provided.

Abstract: Systems, apparatus, articles of manufacture, and methods to detect defects in gate-all-around transistor architectures are disclosed. An apparatus includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine a first contrast to noise ratio (CNR) in a first image of a location on a semiconductor wafer; determine a second CNR in a second image of the location on the semiconductor wafer; and determine whether the location includes a buried defect based on the first CNR and the second CNR.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A flexible warning light includes a lamp housing including a base with a bottom plate, a flexible lamp shell covering base and an accommodation space defined between base and flexible lamp shell, and a light-emitting device mounted in the accommodation space and having at least one light-emitting element on the top of a flexible circuit board of a light-emitting device on the top, and a first heat sink and multiple second heat sinks on the bottom. The flexible lamp shell will elastically deform in accordance with the surface curvature of a preset vehicle body to drive first heat sink and second heat sinks to deform so that the base can be closely attached to the curved surface of the preset vehicle body through the deformation of the first heat sink and the second heat sinks, so as to achieve the effect of being more compliant with the curved vehicle body.

Abstract: A semiconductor device includes a substrate, an active region in the substrate, and a gate structure in the active region. The gate structure includes a bottom conductive layer, a top conductive layer on the bottom conductive layer, and a cap layer on the top conductive layer. A width of the bottom conductive layer is wider than a width of the top conductive layer, and a width of the cap layer is wider than the width of the top conductive layer. The top conductive layer and the bottom conductive layer are made of a same material. A method of forming the semiconductor device is also disclosed.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.

Abstract: A flexible warning light includes a lamp housing including a base with a bottom plate, a flexible lamp shell covering base and an accommodation space defined between base and flexible lamp shell, and a light-emitting device mounted in the accommodation space and having at least one light-emitting element on the top of a flexible circuit board of a light-emitting device on the top, and a first heat sink and multiple second heat sinks on the bottom. The flexible lamp shell will elastically deform in accordance with the surface curvature of a preset vehicle body to drive first heat sink and second heat sinks to deform so that the base can be closely attached to the curved surface of the preset vehicle body through the deformation of the first heat sink and the second heat sinks, so as to achieve the effect of being more compliant with the curved vehicle body.

Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a landing pad layer, a middle patterned dielectric layer, a top patterned dielectric layer, and a plurality of trench conductive layers. The middle patterned dielectric layer is disposed over the landing pad layer, in which the middle patterned dielectric layer includes a plurality of first openings. The top patterned dielectric layer is disposed over the middle patterned dielectric layer, in which the top patterned dielectric layer includes a plurality of second openings substantially aligned with the first openings, respectively. Each of the trench conductive layers is disposed through a portion of one of the second openings and a portion of one of the first openings, and each of the trench conductive layers has two side layers opposite to each other.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate. First and second landing pads are disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and is electrically connected to the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad and the second landing pad, in which the conductive layer covers upper surfaces of the first and second landing pads and has a portion between the first landing pad and the second landing pad.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one of the plurality of bit line contacts is disposed within one of the trenches defined by the substrate, wherein the plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.