Abstract: A semiconductor structure is provided. The semiconductor structure includes a landing pad layer, a middle patterned dielectric layer, a top patterned dielectric layer, and a plurality of trench conductive layers. The middle patterned dielectric layer is disposed over the landing pad layer, in which the middle patterned dielectric layer includes a plurality of first openings. The top patterned dielectric layer is disposed over the middle patterned dielectric layer, in which the top patterned dielectric layer includes a plurality of second openings substantially aligned with the first openings, respectively. Each of the trench conductive layers is disposed through a portion of one of the second openings and a portion of one of the first openings, and each of the trench conductive layers has two side layers opposite to each other.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate. First and second landing pads are disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and is electrically connected to the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad and the second landing pad, in which the conductive layer covers upper surfaces of the first and second landing pads and has a portion between the first landing pad and the second landing pad.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate defining a plurality of trenches; and a plurality of bit line contacts disposed on the substrate, wherein at least one of the plurality of bit line contacts is disposed within one of the trenches defined by the substrate, wherein the plurality of trenches has a first row and a second row, and a pitch of the first row is different from a pitch of the second row.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.

Abstract: A manufacturing method of a semiconductor structure includes forming an active area in a substrate, in which the substrate has an array region and a peripheral region adjacent to the array region. A word line structure is formed in the array region of the substrate. A first protection layer is formed covering the active area and the word line structure. A hard mask stack is formed on the first protection layer. A bit line feature is formed in the first protection layer. After forming the bit line feature, a gate dielectric layer is formed on the active area in the peripheral region of the substrate. A gate electrode layer is formed on the gate dielectric layer.

Abstract: A flow control structure of a water hose joint has: a hose connector, a coupler, a control section, and a hose. The coupler is coupled with the hose connector, the control section is sleeved on the coupler, and the coupler is inserted into the hose, so as to complete a flow control structure of the hose connector. By combining the hose connector with a connecting pipe and rotating the control section to adjust the relative position of the control section and the coupler to change the water flow, which has the effect of simple flow adjustment.

Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in a dielectric layer to expose a source/drain epitaxial layer in a substrate. An aspect ratio of the contact opening is between about 3 and about 10. The method further includes forming a first metal layer in the contact opening and in contact with the source/drain epitaxial layer, forming a barrier layer on the first metal layer, forming a liner layer on the barrier layer, forming second metal layer on the liner layer to partially fill the contact opening, and forming a third metal layer on the second metal layer to fill the contact opening.

Abstract: An image calibration method applied to a wide-angle image and executed by an image calibration apparatus includes applying primary lens distortion correction for the wide-angle image to generate a corrected image, segmenting an foreground image from the corrected image to generate a background image, applying secondary distortion correction for the foreground image based on the pre-defined object to generate a calibrated foreground image, fusing the background image with the calibrated foreground image to generate a fused image, detecting at least one residual empty pixel not overlapped by the calibrated foreground image within the fused image, and utilizing a machine learning algorithm to fill the at least one residual empty pixel of the fused image by extending the background image to provide an output image. The foreground image contains feature pixels relate to a pre-defined object and the background image has empty pixels corresponding to the foreground image.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.

Abstract: A flow control structure of a water hose joint has: a hose connector, a coupler, a control section, and a hose. The coupler is coupled with the hose connector, the control section is sleeved on the coupler, and the coupler is inserted into the hose, so as to complete a flow control structure of the hose connector. By combining the hose connector with a connecting pipe and rotating the control section to adjust the relative position of the control section and the coupler to change the water flow, which has the effect of simple flow adjustment.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.