Abstract: A memory device is provided, including a non-volatile memory array including multiple memory cells, in which the memory cells arranged in a same row are configured to store corresponding weight data and are coupled to a same word line in multiple word lines; a word line driver configured to transmit multiple word line signals according to multiple input data signals to the word lines to perform a compute-in-memory (CIM) operation of the input data signals and the weight data stored in the non-volatile memory array; and an adder tree circuit coupled to the memory cells. Each of the memory cells in the same row is configured to generate a corresponding output voltage of the CIM operation to the adder tree circuit.

Abstract: A package structure includes a package substrate, a package module on the package substrate, a thermal interface material (TIM) layer on the package module, and a package lid on the TIM layer. The package lid includes a package lid foot portion attached to the package substrate, and a package lid plate portion on the package lid foot portion and including a patterned bottom surface having a plurality of recessed portions, wherein at least a portion of the TIM layer is located in the plurality of recessed portions.

Abstract: The disclosure provides a method of treating HIV infection in a human pediatric patient by the administration of cabotegravir or a pharmaceutically acceptable salt thereof, in combination with rilpivirine or a pharmaceutically acceptable salt thereof.

Abstract: An integrated circuit includes a first set of memory cells configured to store a first set of data, a second set of memory cells configured to store a second set of data, a control circuit coupled to the first and second set of memory cells, and being between the first and second set of memory cells, a first set of input output circuits coupled to the first set of memory cells, a second set of IO circuits coupled to the second set of memory cells, a first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits, and a first ECC encoder/decoder circuit configured to correct a first number of errors in the first and second set of data based on the first and second number of ECC bits.

Abstract: Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Abstract: An energy transmission device includes an energy induction element and a coil. The energy induction element includes a first induction portion and a second induction portion. The second induction portion is disposed adjacent to the first induction portion. The coil is disposed adjacent to the energy induction element. The first induction portion and the second induction portion are made of different materials.

Abstract: An integrated circuit includes a first set of memory cells configured to store a first set of data, a second set of memory cells configured to store a second set of data, a first set of input output (IO) circuits coupled to the first set of memory cells, a second set of IO circuits coupled to the second set of memory cells, a first error correction code (ECC) circuit configured to store a first number of ECC bits, a second ECC circuit configured to store a second number of ECC bits; and a first ECC encoder/decoder circuit configured to correct at least a first number of errors in the first set of data and the second set of data based on the first number of ECC bits and the second number of ECC bits.

Abstract: An electromagnetic interference (EMI) filter includes a first magnetic core, a first choke coil, a second choke coil and a second magnetic core. The first magnetic core has an annular portion and a hollow portion passing through the annular portion. The first choke coil is wound around a first portion of the annular portion, and the second choke coil is wound around a second portion of the annular portion. The first portion is opposite to the second portion. The second magnetic core is arranged in the hollow portion, and the annular portion has at least one recessed portion connected to the second magnetic core.

Abstract: The embodiments of the disclosure provide an image measurement method and an image processing device. The method comprises: obtaining an input image and a plurality of reference line segments in the input image; encoding the input image into a sequence vector, and integrating the sequence vector and a positional encoding vector into a first input vector; using a transformer encoder to generate a second input vector based on the first input; using a transformer decoder to generate a predicted offset result corresponding to each of a plurality of to-be-measured line segments based on the second input vector and query information; and generating a measurement result of each to-be-measured line segment based on the predicted offset result of each to-be-measured line segment.

Abstract: A memory device and array architecture feature transmission gates and repeaters to enhance signal integrity and performance. The device includes multiple memory segments, each connected to a decoder through transmission gates, and a repeater circuit positioned along word lines. Memory cells within the segments can be eFuse cells in various configurations, including 2T/1R and 1T/1R. The repeaters, designed as two-stage inverters with PMOS and NMOS transistors, are strategically placed to ensure robust signal propagation. The memory array comprises multiple word and bit lines, with repeaters separating adjacent memory cells, and includes decoders for voltage level shifting. The architecture supports various threshold voltage repeaters, ensuring flexibility and efficiency in different operating conditions.

Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: The present invention provides a DC system protection apparatus with a communication resetting function, which includes at least one load, at least one DC power supply system, a DC solid-state circuit breaker, a current sensor, a reset/break controller and a reset communication module. The at least one DC power supply system is connected to the at least one load. The DC solid-state circuit breaker is connected in series with the at least one load and the at least one DC power supply system. The current sensor is connected in series with the DC solid-state circuit breaker, the at least one load and the at least one DC power supply system. The reset/break controller is connected to the current sensor, and controls breaking and resetting of the DC solid-state circuit breaker. The reset communication module is connected to the reset/break controller.

Abstract: The present disclosure provides a semiconductor device, which includes a plurality of programmable elements and a plurality of programming devices. The plurality of programmable elements are arranged in a two-dimensional array having a plurality of word line groups and a plurality of bit-line groups. The plurality of programming devices each is electrically connected to a respective programmable element among the programmable elements. Each bit-line group comprises at least two bit lines that are shunted.

Abstract: A resistive memory structure includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, a top electrode layer disposed on the switching layer, and an oxidized protection layer disposed on a sidewall of the memory stack structure. A spacer is located around the memory stack structure. The spacer covers the oxidized protection layer. A dielectric buffer layer is disposed on the spacer.

Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.

Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.

Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: A memory device includes a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion, wherein the first and second portions are disposed next to each other along a first lateral direction; a first driver circuit disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion and the first driver circuit along the first lateral direction; and a second driver circuit disposed next to both of the first and second portions along a second lateral direction perpendicular to the first lateral direction. The OTP memory cells of the first portion are associated with a first electrical/physical characteristic and the OTP memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.