Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: The present invention provides a DC system protection apparatus with a communication resetting function, which includes at least one load, at least one DC power supply system, a DC solid-state circuit breaker, a current sensor, a reset/break controller and a reset communication module. The at least one DC power supply system is connected to the at least one load. The DC solid-state circuit breaker is connected in series with the at least one load and the at least one DC power supply system. The current sensor is connected in series with the DC solid-state circuit breaker, the at least one load and the at least one DC power supply system. The reset/break controller is connected to the current sensor, and controls breaking and resetting of the DC solid-state circuit breaker. The reset communication module is connected to the reset/break controller.

Abstract: The present disclosure provides a semiconductor device, which includes a plurality of programmable elements and a plurality of programming devices. The plurality of programmable elements are arranged in a two-dimensional array having a plurality of word line groups and a plurality of bit-line groups. The plurality of programming devices each is electrically connected to a respective programmable element among the programmable elements. Each bit-line group comprises at least two bit lines that are shunted.

Abstract: A resistive memory structure includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, a top electrode layer disposed on the switching layer, and an oxidized protection layer disposed on a sidewall of the memory stack structure. A spacer is located around the memory stack structure. The spacer covers the oxidized protection layer. A dielectric buffer layer is disposed on the spacer.

Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.

Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.

Abstract: A memory device is provided and including a memory array including multiple memory cells each including a memory unit; and a first number of first transistors coupled in series between the memory unit and a first voltage terminal. The memory device further includes a voltage generating circuit coupled between the memory array and a second voltage terminal. The voltage generating circuit includes multiple voltage divider circuits each including a second number of second transistors coupled in series to a corresponding one in multiple data lines to a corresponding column of the memory cells.

Abstract: A memory device includes a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion, wherein the first and second portions are disposed next to each other along a first lateral direction; a first driver circuit disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion and the first driver circuit along the first lateral direction; and a second driver circuit disposed next to both of the first and second portions along a second lateral direction perpendicular to the first lateral direction. The OTP memory cells of the first portion are associated with a first electrical/physical characteristic and the OTP memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.

Abstract: A memory device is provided, including a non-volatile memory array including multiple memory cells, in which the memory cells arranged in a same row are configured to store corresponding weight data and are coupled to a same word line in multiple word lines; a word line driver configured to transmit multiple word line signals according to multiple input data signals to the word lines to perform a compute-in-memory (CIM) operation of the input data signals and the weight data stored in the non-volatile memory array; and an adder tree circuit coupled to the memory cells. Each of the memory cells in the same row is configured to generate a corresponding output voltage of the CIM operation to the adder tree circuit.

Abstract: The present invention provides a DC system protection apparatus with a communication resetting function, which includes at least one load, at least one DC power supply system, a DC solid-state circuit breaker, a current sensor, a reset/break controller and a reset communication module. The at least one DC power supply system is connected to the at least one load. The DC solid-state circuit breaker is connected in series with the at least one load and the at least one DC power supply system. The current sensor is connected in series with the DC solid-state circuit breaker, the at least one load and the at least one DC power supply system. The reset/break controller is connected to the current sensor, and controls breaking and resetting of the DC solid-state circuit breaker. The reset communication module is connected to the reset/break controller.

Abstract: A package structure is provided. The package structure includes a substrate, a die bonded to the substrate, a lid disposed over the die and the substrate, and an interface structure sandwiched between the die and the lid and including a first thermal interface material disposed at corners of a top surface of the die, and a second thermal interface material disposed a rest of the top surface of the die. A Young's modulus of the first thermal interface material is smaller than a Young's modulus of the second thermal interface material.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal, a frequency divider configured to receive the clock signal and generate a reduced frequency signal indicative of a skew of a first multi-phase clock signal, and a delay line control circuit configured to adjust the skew of the first multi-phase clock signal by comparing the reduced frequency signal with a predetermined duty cycle, and generating a control signal to modify a delay applied to the first multi-phase clock signal.

Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The present invention provides for a genetically modified host cell comprising a first polypeptide capable of active transport of urea into the host cell and/or a second polypeptide capable of degrading urea into ammonia and carbon dioxide, wherein the genetically modified host cell is capable of degrading urea into ammonia and carbon dioxide. The genetically modified host cell in a medium comprising urea, a calcium salt or calcium ion, and a phosphate is capable of producing calcium phosphate.

Abstract: Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Abstract: A semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.