Patents by Inventor Yu-Wen Wang

Yu-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Publication number: 20240145511
    Abstract: An image sensor includes a first sensing unit. The first sensing unit includes a pair of photodiodes formed in a substrate and spaced by a deep trench isolation structure, an outer grid over the pair of photodiodes, a color filter filled in the outer grid, and an inner grid disposed in the color filter. The color filter overlaps the pair of photodiodes. The inner grid includes a first spacer, wherein the first spacer is rotated relative to the deep trench isolation structure.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Jian-Wen LUO, Yu-Chi CHANG, Zong-Ru TU, Po-Hsiang WANG
  • Patent number: 11961769
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20240119200
    Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11955379
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
  • Patent number: 11956948
    Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 11944970
    Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 2, 2024
    Assignees: INSTANT NANOBIOSENSORS, INC., INSTANT NANOBIOSENSORS CO., LTD.
    Inventors: Yu-Chung Huang, Yi-Li Sun, Ting-Chou Chang, Jhy-Wen Wu, Nan-Kuang Yao, Lai-Kwan Chau, Shau-Chun Wang, Ying Ting Chen
  • Fan
    Patent number: 11946483
    Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
  • Patent number: 11945918
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 2, 2024
    Assignee: Novoloop, Inc.
    Inventors: Jia Yun Yao, Yu Wen Wang, Tapaswy Muppaneni, Ruja Shrestha, Jennifer Le Roy, Garret D. Figuly
  • Publication number: 20240096630
    Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240089573
    Abstract: A photosensitive assembly includes a circuit board. The circuit board has a first surface, a second surface opposite to the first surface, and a first through hole extending through the first surface and the second surface. A photosensitive chip is disposed on the second surface. The photosensitive chip has a photosensitive area and a non-photosensitive area connected to the photosensitive area, the non-photosensitive area is electrically connected to one side of the second surface, and the photosensitive area is exposed from the first through hole. A reinforcing plate is disposed on the first surface. A thermal conductive layer is disposed on the photosensitive chip, and the thermal conductive layer includes a silica gel or a metal.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Inventors: KUN LI, SHIN-WEN CHEN, BO-YING ZHU, YU-SHUAI LI, JIAN-CHAO SONG, WU-TONG WANG
  • Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • Patent number: 11923437
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20240072170
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
  • Publication number: 20240074041
    Abstract: A circuit board includes a substrate and a metallic layer. A first area and at least one second area are defined on a portion of the substrate, the second area is located outside the first area. The metallic layer includes first test lines disposed on the first area and second test lines disposed on the second area. A first test pad of each of the first test lines has a first width, and a second test pad of each of the second test lines has a second width. The second width is greater than the first width such that probes of an electrical testing tool can contact the first and second test pads on the circuit board correctly during electrical testing.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Inventors: Gwo-Shyan Sheu, Kuo-Liang Huang, Hsin-Hao Huang, Pei-Wen Wang, Yu-Chen Ma
  • Publication number: 20240069304
    Abstract: A voice coil motor held immobile by magnetic attraction when not in use for photography purposes includes a base, a magnet fixed thereto, a carrier, a magnetic member, and a coil. The magnetic member is fixed to the carrier and is attracted by a permanent magnetic field (first MF) of the magnet on the base. The coil is fixed to the carrier and the magnetic member. When the voice coil motor is powered on, the coil generates a second magnetic field (second MF) opposing the first MF. The second MF reduces or eliminates the attractive force of the first MF of the magnet, to separate the carrier and its fittings and allow them to work freely. A lens module and an electronic device are further provided.
    Type: Application
    Filed: September 30, 2022
    Publication date: February 29, 2024
    Inventors: YU-SHUAI LI, SHIN-WEN CHEN, KUN LI, JIAN-CHAO SONG, WU-TONG WANG, DING FENG
  • Publication number: 20240057346
    Abstract: Device structures and methods for forming the same are provided. A device structure according to the present disclosure includes a first electrode and a second electrode disposed over an etch stop layer (ESL), a first dielectric layer disposed between the first electrode and the second electrode, a phase-change material layer disposed over the first electrode, the first dielectric layer and the second electrode, an insulator layer disposed over the phase-change material layer, a metal feature disposed over the insulator layer, and a second dielectric layer disposed over the insulator layer, the first electrode, the second electrode, and the metal feature.
    Type: Application
    Filed: January 6, 2023
    Publication date: February 15, 2024
    Inventors: Fu-Ting Sung, Tsung-Hsueh Yang, Chang-Ming Wu, Chang-Chih Huang, Yu-Wen Wang, Kuo-Chyuan Tzeng
  • Publication number: 20230420567
    Abstract: A method for forming a multi-gate semiconductor structure is provided. A substrate including a fin structure is received. First portions of the fin structure are removed to expose a source/drain region of the fin structure. A semiconductor layer is formed in the source/drain region. Second portions of the fin structure are removed to expose a channel region of the fin structure. A surface of the channel region of the fin structure is cleaned. An interfacial layer is formed over the cleaned surface of the channel region of the fin structure.
    Type: Application
    Filed: June 26, 2022
    Publication date: December 28, 2023
    Inventors: CHUN-MING YANG, YU-JIUN PENG, YU-WEN WANG