Abstract: A fingerprint identification module, a manufacturing method thereof and an electronic device are disclosed.

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

Abstract: A piezoelectric device includes: a base having at least one hole, a heat conductive portion disposed in the at least one hole and in contact with a wall of the at least one hole, and at least one piezoelectric sensor disposed on the base. A thermal conductivity of the heat conductive portion is greater than a thermal conductivity of the base. Each piezoelectric sensor includes: a first electrode, a piezoelectric pattern made of a piezoelectric material and a second electrode that are sequentially stacked in a thickness direction of the base.

Abstract: A driving backplane includes a base, and a pixel driving circuit, a first electrode and a first piezoelectric block that are disposed in the sub-pixel region. The pixel driving circuit is disposed on the base. The first electrode is disposed at a side of the pixel driving circuit away from the base. The first electrode includes a first sub-electrode pattern and a second sub-electrode pattern that are in a same layer and are spaced apart to be insulated from each other, and the first sub-electrode pattern is electrically connected to the pixel driving circuit. The first piezoelectric block is disposed between the pixel driving circuit and the first electrode, and the first sub-electrode pattern and the second sub-electrode pattern are in contact with the first piezoelectric block.

Abstract: Embodiments of the present disclosure provide a method for manufacturing a fingerprint recognition method, a fingerprint recognition module, and a display device. The method for manufacturing the fingerprint recognition module includes: providing a backplane; forming a bonding terminal in a bonding area of the backplane; forming a sensing electrode in a fingerprint recognition area of the backplane; forming an insulation layer cladding the bonding terminal in the bonding area, and forming a piezoelectric material layer in the fingerprint recognition area, where an orthographic projection of the piezoelectric material layer on the backplane coincides with an orthographic projection of the sensing electrode on the backplane; performing polarization processing on the piezoelectric material layer; and peeling off the insulation layer.

Abstract: A detection substrate, a preparation method thereof, a detection device and a detection method are provided. A detection substrate includes a base substrate, wherein the base substrate includes multiple through holes, and electrode columns are embedded in the multiple through holes; the base substrate comprises a detection region and a bonding pad region, the detection region includes a driving circuit, and the bonding pad region is provided with bonding pads; and the bonding pads are connected with the electrode columns through the driving circuit.

Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: a first medium and a first spacer wall between the first substrate and the second substrate, wherein the first sub-panel has filter pixels arranged at intervals, the first spacer wall is black and arranged along spaces between filter pixels, and a dielectric coefficient of the first spacer wall is greater than that of the first medium; and a second sub-panel on a light emergent side of the first sub-panel and including a second medium and a second spacer wall between the third substrate and the fourth substrate, wherein the second sub-panel has display pixels arranged at intervals, the second spacer wall is black and arranged along spaces between display pixels, and a dielectric coefficient of the second spacer wall is greater than that of the second medium.

Abstract: A filter structure and a method for manufacturing the same, and a display device. The filter structure includes a base substrate and a plurality of filter units positioned on the base substrate, at least part of the filter units including a quantum dot filter layer. The filter units further include a reflective structure whose orthographic projection on the base substrate surrounds the orthographic projection of the quantum dot filter layer on the base substrate. A distance between a plane of the reflective structure away from the base substrate and the base substrate is greater than a distance between a plane of the quantum dot filter layer close to the base substrate and the base substrate.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: The disclosure discloses a backboard, a display device, and a method for fabricating the same, and the backboard includes: a backboard body; and a plurality of LED installation mounts arranged in an array on the backboard body, wherein each of the plurality of LED installation mounts includes at least two lead-out electrodes to be connected with LED pins, and a coil structure around each of the at least two lead-out electrodes, wherein the coil structure is configured to produce a magnetic field upon being powered on. The coils can be formed on the backboard body in the backboard to absorb electrodes of LEDs to thereby position them precisely so as to transfer the LEDs in a mass manner with a high good yield ratio, and the lead-out electrodes can be powered on to thereby detect abnormally operating LEDs.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided, in the field of display technology. The display substrate includes a base substrate, and a thin-film transistor, a light-emitting device, an encapsulation structure, and a conductive film layer sequentially disposed on the base substrate in a direction away from the base substrate. Since the display substrate includes a conductive film layer on a side of the encapsulation structure away from the base substrate, when the protective film layer on the side of the conductive film layer away from the base substrate is peeled off, static electricity generated by the separation of the film layer can be released to the conductive film layer, avoiding electron transition to the active layer of the thin-film transistor in the display substrate to cause offset of the threshold voltage of the thin-film transistor. The display brightness uniformity of the display substrate can be ensured.

Abstract: The present invention provides methods for inhibiting complement activation and uses thereof. More specifically, the present invention provides methods for inhibiting complement activation using inorganic polyphosphates of at least 10 phosphate units. The polyphosphates inhibit complement activation by one or more of: binding to the C6 complement protein, C1-esterase inhibitor (C1-inh), factor H or factor B; enhancing the activity of C1-inh; interfering with C1s-mediated cleavage of C2; destabilizing the C5b-6 complement protein complex; interfering with C5b,6 interaction with C7; interfering with binding of C5b-7 to a cell membrane; interfering with integration of C5b-7 into a cell membrane; interfering with binding of C5b-8 to a cell membrane; interfering with integration of C5b-8 into a cell membrane; destabilizing the membrane attack complex (MAC); or reducing the amount of C5b-9 deposited on a cell surface.

Abstract: The present invention provides methods for inhibiting complement activation and uses thereof. More specifically, the present invention provides methods for inhibiting complement activation using inorganic polyphosphates of at least 10 phosphate units. The polyphosphates inhibit complement activation by one or more of: binding to the C6 complement protein, C1-esterase inhibitor (C1-inh), factor H or factor B; enhancing the activity of C1-inh; interfering with C1s-mediated cleavage of C2; destabilizing the C5b-6 complement protein complex; interfering with C5b,6 interaction with C7; interfering with binding of C5b-7 to a cell membrane; interfering with integration of C5b-7 into a cell membrane; interfering with binding of C5b-8 to a cell membrane; interfering with integration of C5b-8 into a cell membrane; destabilizing the membrane attack complex (MAC); or reducing the amount of C5b-9 deposited on a cell surface.

Abstract: A method for protecting a master boot record in a solid state drive, comprising the steps of (A) receiving a plurality of input/output requests from a host device, (B) determining whether one or more of the input/output requests is read/written to a first of a plurality of logical block addresses of the solid state drive and (C) writing an entry to a table for each of the input/output requests read/written to the first of the logical block addresses. The table (i) is separate from the first of the logical block addresses and (ii) is used to recover errors in the first of the logical block addresses.