Patents by Inventor Zhen Huang

Zhen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959941
    Abstract: A probe card includes a flexible inorganic material layer, a metal micro structure, and a circuit board. The flexible inorganic material layer has a first surface and a second surface opposite to each other. The metal micro structure is disposed on the first surface. The circuit board is disposed on the second surface, and the circuit board is electrically connected to the metal micro structure. The test signal is adapted to be conducted to the circuit board through the flexible inorganic material layer.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: April 16, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Chieh Chou, Meng-Chi Huang, Tune-Hune Kao, Yue-Zhen Huang
  • Publication number: 20240120651
    Abstract: Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 11, 2024
    Inventors: Zhen Zhou, Tae Young Yang, Timo Huusari, Renzhi Liu, Wei Qian, Mengyuan Huang, Jason Mix
  • Patent number: 11955552
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Shih-Chuan Chiu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240108784
    Abstract: A hydrogel for cell-laden bioprinting, bioink, and a preparation method and an application thereof, relates to the technical field of biomedical polymer hydrogels. The hydrogel for cell-laden bioprinting is polymer gel formed by adding a cell-specific material into a matrix of alginate and gelatin and crosslinking and curing, wherein the cell-specific material is polypeptide selected according to different laden cells. The structures printed using the hydrogel may have the advantages such as adjustable mechanical properties, adjustable porosity, high biocompatibility, high printing accuracy, and high customizability, which may widely support the printing of human tissues and organs such as spinal cord, cartilage, and heart, and has good prospects for applications in tissue repair, organ transplantation and so on.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 4, 2024
    Applicants: SHANDONG UNIVERSITY, YANSHAN UNIVERSITY
    Inventors: Chuanzhen HUANG, Zhuang CHEN, Hanlian LIU, Peng YAO, Zhenyu SHI, Dun LIU, Hongtao ZHU, Bin ZOU, Zhen WANG, Minting WANG, Longhua XU, Shuiquan HUANG, Meina QU, Zhengkai XU, Yabin GUAN
  • Patent number: 11947966
    Abstract: A computer-implemented method includes preprocessing, by a compiler, a plurality of macros in a computer program. Preprocessing a macro includes identifying a compile time condition associated with the macro. Preprocessing the macro further includes determining a current value of the compile time condition at the time of compiling a computer instruction and a previous value of the compile time condition. Preprocessing the macro further includes determining a set of computer instructions enclosed by the macro. The method further includes storing a macro information record that includes the compile time condition, the current value and the previous value of the compile time condition, and an identification of the set of computer instructions enclosed by the macro.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Wen Ji Huang, Xiao Ling Chen, Wen Bin Han, Sheng Shuang Li, Xiao Zhen Zhu
  • Patent number: 11948595
    Abstract: Provided is a method for detecting audio, which includes acquiring audio file data; determining attribute detection data corresponding to the audio file data; and generating a voice detection result corresponding to the audio file data by voice violation detection on the attribute detection data by a fully connected network model. A device for detecting audio and a non-transitory computer-readable storage medium are also provided.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 2, 2024
    Assignee: BIGO TECHNOLOGY PTE. LTD.
    Inventors: Zhen Li, Zhenchuan Huang, Yu Zou
  • Patent number: 11948879
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240099311
    Abstract: A virulence factor FsPL gene from the sugarcane pokkah boeng disease and use thereof are provided. The virulence factor FsPL gene from the sugarcane pokkah boeng disease has a sequence set forth in SEQ ID NO: 1. The present invention reveals a gene FsPL that is related to the pathogenicity of F. sacchari. Preliminary analysis shows that the deletion of the gene affects the ability of hyphae to penetrate and further affects the pathogenicity of pathogens. This provides a basis for the molecular mechanism of the pathogen infection and pathogenic process.
    Type: Application
    Filed: March 16, 2023
    Publication date: March 28, 2024
    Applicant: GUANGXI UNIVERSITY
    Inventors: Zhenzhen DUAN, Wei YAO, Muqing ZHANG, Caixia WANG, Zhen HUANG, Yixue BAO, Huixue LI
  • Publication number: 20240103328
    Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: March 28, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Zhen Zhang, Fuqiang Li, Zhenyu Zhang, Yunping Di, Lizhong Wang, Zheng Fang, Jiahui Han, Yawei Wang, Chenyang Zhang, Chengfu Xu, Ce Ning, Pengxia Liang, Feihu Zhou, Xianqin Meng, Weiting Peng, Qiuli Wang, Binbin Tong, Rui Huang, Tianmin Zhou, Wei Yang
  • Publication number: 20240096997
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed in a PFET region and a second source/drain region disposed in an NFET region. The second source/drain region comprises a dipole region. The structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. The first, second, and third silicide layers include different materials. The structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.
    Type: Application
    Filed: January 15, 2023
    Publication date: March 21, 2024
    Inventors: Po-Chin Chang, Lin-Yu Huang, Li-Zhen Yu, Yuting Cheng, Sung-Li Wang, Pinyen Lin
  • Publication number: 20240087949
    Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Yu-Ming Lin, Lin-Yu Huang
  • Publication number: 20240087861
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Patent number: 11929321
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11927937
    Abstract: Disclosed is a prediction method for tool remaining life of a numerical control machine tool based on a hybrid neural model, including: constructing a hybrid neural network model, specifically including the following steps: constructing sample data according to the sampling frequency of tool data; obtaining a first feature vector representing the tool life by utilizing a convolutional neural network and a long short-term memory network; generating working condition signals of sampling points into a second feature vector representing the tool life by utilizing an NFM neural network; and inputting a current working time of a tool and the acquired feature vectors into a multi-layer perceptron for fusion to predict the tool life.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF INDUSTRIAL INTERNET, CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Qingqing Huang, Yan Han, Zhen Kang, Yan Zhang, Ping Wang
  • Patent number: 11928446
    Abstract: A method, apparatus, and a non-transitory computer-readable storage medium for generating heterogenous platform code. The method may obtain a neural network model. The neural network model may be programed to run on at least one platform. The method may also obtain an initial intermediate representation (IR) code by encoding the neural network model, and obtain a target IR code by adding decorations to the initial IR code based on a target platform. The method may also output an executable code optimized to run on the target platform by decoding the target IR code.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 12, 2024
    Assignee: KWAI INC.
    Inventors: Zhen Peng, Yang Liu, Hanxian Huang, Yongxiong Ren, Jishen Yang, Lingzhi Liu, Xin Chen
  • Patent number: 11923408
    Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240073622
    Abstract: A sound generator provided in the present disclosure includes a frame, a magnetic circuit unit, and a first vibration unit and a second vibration unit arranged on two sides of the magnetic circuit unit. The magnetic circuit unit includes a first central magnetic yoke in the middle, a central magnet fixed to the first central magnetic yoke, a magnetic component arranged around the central magnet and fixed to the frame, and a connecting portion connecting the first central magnetic yoke to the magnetic component. The central magnet includes a first magnet portion fixed to the first central magnetic yoke and a second magnet portion fixed to the side of the first magnet portion away from the first central magnetic yoke, a projection area of the first magnet portion along a vibrating direction is greater than a projection area of the second magnet portion along the vibrating direction.
    Type: Application
    Filed: January 16, 2023
    Publication date: February 29, 2024
    Inventors: Xuedong Lv, Xiaoqiong Feng, Kun Yang, Zhen Huang, Yi Shao
  • Publication number: 20240071102
    Abstract: Provided are a lane line recognition method, an electronic device and a storage medium, relating to a technical field of artificial intelligence, in particular to technical fields of intelligent transportation, automatic driving and deep learning. The lane line recognition method includes: extracting a basic feature of an original image; recognizing at least one lane line node in the original image by using the basic feature of the original image; extracting a local feature from the basic feature of the original image by using the at least one lane line node; fusing the basic feature and the local feature; and recognizing a lane line in the original image based on a fused result.
    Type: Application
    Filed: January 3, 2023
    Publication date: February 29, 2024
    Inventors: Bin WU, Kai ZHONG, Tongbin ZHANG, Jianzhong YANG, Zhen LU, Deguo XIA, Jizhou HUANG
  • Publication number: 20240073615
    Abstract: The present disclosure discloses a sound device includes a frame, a magnet system, and a first vibration system and a second vibration system arranged on two sides of a magnet system. The magnet system includes a first central yoke, a central magnet mounted on the first central yoke, a side yoke surrounding the central magnet and fixed to the frame, and a connection portion connecting the first central yoke and the side yoke. The side yoke includes a first side yoke fixed to the frame and a second side yoke bending and extending from an edge of the first side yoke towards the central magnet; the connection portion connects the first central yoke and the second side yoke. The sound device in the present disclosure has higher magnetic ability and miniaturization ability.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: Xuedong Lv, Xiaoqiong Feng, Kun Yang, Zhen Huang, Yi Shao
  • Publication number: 20240070120
    Abstract: In one example method, a server obtains compressed data, where the compressed data includes at least a first part and a second part, and where the compressed data is sorted based on popularity values of parts of the compressed data, and a popularity value of a part of the compressed data is greater than a popularity value of a subsequent part of the compressed data. The server decompresses the first part, and decompresses the second part after decompressing the first part, where a popularity value of the first part is greater than a popularity value of the second part.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Zhen CHENG, Zengshi HUANG