Patents by Inventor Zheng Yang

Zheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FULLY STRAINED CHANNEL
    Publication number: 20190096997
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. MORE, Huai-Tei YANG, Zheng-Yang PAN, Shih-Chieh CHANG, Chun-Chieh WANG, Cheng-Han LEE
  • 2-morpholin-4,6-disubstituted pyrimidine derivative, and preparation method and pharmaceutical use thereof
    Patent number: 10227324
    Abstract: Disclosed is a 2-morpholin-4,6-disubstituted pyrimidine derivative as shown in formula (1) below, and a pharmaceutically acceptable salt, solvate, stereoisomer or prodrug thereof, and a pharmaceutical composition thereof and a use thereof, wherein the definition of each group is as shown in the description. The compound has a PI3K kinase inhibition activity, and has a relatively high inhibitive ability and a low cytotoxicity against PIK3CA mutant breast cancer cell strains T47D and MCF-7.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 12, 2019
    Assignees: SHANGHAI HAIYAN PHARMACEUTICAL TECHNOLOGY CO., LTD., YANGTZE RIVER PHARMACEUTICAL GROUP CO., LTD.
    Inventors: Sida Shen, Xiaojing Ni, Zhiyuan Zhang, Zheng Yang, Xiangyu He, Weiwei Wang, Fusheng Zhou
  • STRUCTURE AND METHOD FOR HIGH-K METAL GATE
    Publication number: 20190067457
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 28, 2019
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • FinFET Device and Methods of Forming Same
    Publication number: 20190067011
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: February 28, 2019
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • Implantations for Forming Source/Drain Regions of Different Transistors
    Publication number: 20190035694
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Shih-Chieh Chang
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20190006507
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: January 3, 2019
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Formation method and structure semiconductor device with source/drain structures
    Patent number: 10164100
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • COMPARATOR FOR DOUBLE RAMP ANALOG TO DIGITAL CONVERTER
    Publication number: 20180324378
    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 8, 2018
    Inventors: Hiroaki Ebihara, Zheng Yang
  • COMPARATOR FOR DOUBLE RAMP ANALOG TO DIGITAL CONVERTER
    Publication number: 20180324379
    Abstract: A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.
    Type: Application
    Filed: July 13, 2018
    Publication date: November 8, 2018
    Inventors: Hiroaki Ebihara, Zheng Yang
  • FORMATION METHOD AND STRUCTURE OF SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN STRUCTURES
    Publication number: 20180294357
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • Comparator for double ramp analog to digital converter
    Patent number: 10079990
    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: September 18, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroaki Ebihara, Zheng Yang
  • ANTIBODIES AGAINST OX40 AND USES THEREOF
    Publication number: 20180237534
    Abstract: Provided herein are antibodies, or antigen binding portions thereof, that bind to OX40. Also provided are uses of these proteins in therapeutic applications, such as in the treatment of cancer. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain variable region of the antibodies, and vectors comprising the polynucleotides encoding the heavy and/or light chain variable region of the antibodies.
    Type: Application
    Filed: May 26, 2016
    Publication date: August 23, 2018
    Inventors: Zhehong CAI, Indrani CHAKRABORTY, Marie-Michelle Navarro GARCIA, Thomas D. KEMPE, Alan J. KORMAN, Alexander T. KOZHICH, Hadia LEMAR, Mark MAURER, Christina Maria MILBURN, Michael QUIGLEY, Maria RODRIGUEZ, Xiang SHAO, Mohan SRINIVASAN, Brenda L. STEVENS, Kent THUDIUM, Susan Chien-Szu WONG, Jochem GOKEMEIJER, Xi-Tao WANG, Han CHANG, Christine HUANG, Maria JURE-KUNKEL, Zheng YANG, Yan FENG, Patrick GUIRNALDA, Nils LONBERG, Bryan C. BARNHART, Aaron P. YAMNIUK, Karla A. HENNING, Michelle Minhua HAN, Ming LEI, Liang SCHWEIZER, Sandra V. HATCHER, Arvind RAJPAL, Praveen AANUR, Mark J. SELBY
  • Formation method of semiconductor device structure with semiconductor nanowire
    Patent number: 10043665
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang, Chandrashekhar Prakash Savant
  • Feedback Capacitor And Method For Readout Of Hybrid Bonded Image Sensors
    Publication number: 20180220095
    Abstract: A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 2, 2018
    Inventors: Rui WANG, Hiroaki EBIHARA, Zheng YANG, Chun-Ming TANG, Chao-Fang TSAI, Tiejun DAI
  • Two Stage Amplifier Readout Circuit In Pixel Level Hybrid Bond Image Sensors
    Publication number: 20180220094
    Abstract: A hybrid bonded image sensor has a photodiode die with macrocells having at least one photodiode and a bond contact; a supporting circuitry die with multiple supercells, each supercell having at least one macrocell unit having a bond contact coupled to the bond contact of a macrocell of the photodiode die. Each macrocell unit lies within a supercell and has a reset transistor adapted to reset photodiodes of the macrocell of the photodiode die. Each supercell has at least one common source amplifier adapted to receive signal from the bond contact of a selected macrocell unit of the supercell, the common source amplifier coupled to drive a column line through a selectable source follower. In embodiments, the common source amplifiers of several supercells drive the selectable source follower through a distributed differential amplifier.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 2, 2018
    Inventors: Zheng YANG, Hiroaki EBIHARA, Chun-Ming TANG, Chao-Fang TSAI, Rui WANG, Tiejun DAI
  • Structure of semiconductor device with source/drain structures
    Patent number: 10026840
    Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Image sensor with fast intra-frame focus
    Patent number: 10015388
    Abstract: A method of focusing an image sensor includes scanning a first portion of an image frame from an image sensor a first time at a first rate to produce first focus data. A second portion of the image frame from the image sensor is scanned at a second rate to read image data from the second portion. The first rate is greater than the second rate. The first portion of the image frame is scanned a second time at the first rate to produce second focus data. The first focus data and the second focus data are compared, and the focus of a lens is adjusted in response to the comparison of the first focus data and the second focus data.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 3, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Tiejun Dai, Eiichi Funatsu, Donghui Wu, Zheng Yang, Xiao Xie
  • Semiconductor Device and Method
    Publication number: 20180174913
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: June 21, 2018
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Image sensor floating diffusion boosting by transfer gates
    Patent number: 9998696
    Abstract: A shared pixel includes a plurality of transfer gates coupled between respective photodiodes and a shared floating diffusion. Each transfer gate is coupled to receive a transfer control signal to independently control a transfer of the image charge from the corresponding photodiodes to the shared floating diffusion. Each transfer control signal is set to one of an ON value, a first OFF value, and a second OFF value. One of the control signals that is coupled to an active transfer gate is set to the ON value during a transfer operation. The control signals coupled to idle transfer gates are set to the first OFF value during a reset period prior to the transfer operation, and are set to the second OFF value during the transfer operation.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 12, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventor: Zheng Yang
  • Dopant Concentration Boost in Epitaxially Formed Material
    Publication number: 20180151730
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 31, 2018
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee