Patents by Inventor Zheng Yang

Zheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200396403
    Abstract: An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Hiroaki Ebihara, Zheng Yang
  • Patent number: 10867799
    Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang, Shahaji B. More
  • Publication number: 20200365720
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10837770
    Abstract: A measuring device for measuring an object. The measuring device includes a distance measuring unit having a beam emission unit generating a measurement radiation having a defined wavelength spectrum and a detector detecting the measurement radiation reflected on the object surface, the detector having at least one first sensor. The distance measuring unit generates distance measured data and reflection measured data as first distance measured data by emitting the measurement radiation and detecting the reflected measurement radiation according to the principle of triangulation. The measurement radiation is generated using a wavelength spectrum such that a fluorescence is excitable by an interaction of the measurement radiation with the object material to emit fluorescent light, wherein a spectrum of the fluorescent light and the wavelength spectrum of the measurement radiation are different.
    Type: Grant
    Filed: June 15, 2019
    Date of Patent: November 17, 2020
    Assignee: HEXAGON TECHNOLOGY CENTER GMBH
    Inventors: Thomas Jensen, Zheng Yang, Johan Stigwall
  • Patent number: 10834347
    Abstract: A multiple IC, buffered, image sensor has a first IC with pixels, selection transistors, and interconnect coupling selected pixels with first inter-die bond pads that convey image data to a second IC having logic and ADCs. The ADCs having inputs coupled to selected pixels and outputting through-silicon vias and inter-die bond pads to a third IC coupled to buffer raw image data in DRAM. A method includes capturing images with array pixel IC divided into sub-arrays each coupled to a separate, associated, ADC through inter-die bonds, scanning the sub-arrays and converting the image data to digital image data; and transferring the digital image data over inter-die bonds into buffers in DRAM.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 10, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Taehyung Jung, Hoon Ryu, Zheng Yang, Hyunsu Yoon, Chia-Ming Chen
  • Patent number: 10824880
    Abstract: A system for detecting a surrounding object may receive, from a camera, a first image including a plurality of pixels relating to one or more objects and receive, from one or more LiDARs, a first point set including a plurality of points corresponding to the plurality of pixels. The system may also, based on the first point set, determine 3D coordinates and reflection intensities of the plurality of points, based on which the system may generate a segment result by classifying the plurality of points. The system may further transform the 3D coordinates of the plurality of points into 2D coordinates and determine an object type of the one or more objects based on the 2D coordinates, the 3D coordinates, the segment result, and the first image.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: November 3, 2020
    Assignee: BEIJING VOYAGER TECHNOLOGY CO., LTD.
    Inventors: Weilong Yao, Zenan Meng, Jian Liu, Hao Zhang, Shen Tan, Yehe Cai, Zheng Yang
  • Patent number: 10819936
    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 27, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroaki Ebihara, Zheng Yang, Rui Wang, Teijun Dai
  • Publication number: 20200326988
    Abstract: Certain aspects of the present disclosure provide techniques for maintaining an application through an execution platform. An example method generally includes receiving a first workflow definition of a plurality of workflow definitions associated with an application. The first workflow definition may be a workflow defining a build operation for building the application. The first workflow definition is executed to build the application by retrieving an executable binary from a binary repository, retrieving source code for the application binary from an application source code repository, building the application binary by executing the executable binary on the retrieved source code, and storing the application binary in the binary repository. A second workflow definition is received to execute the application. The second workflow is executed to execute the application by retrieving the application binary from the binary repository, and executing the retrieved application binary to run the application.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Edward K. LEE, Hong WANG, Ying XIE, Zheng YANG
  • Publication number: 20200300776
    Abstract: Disclosed herein are devices, systems, methods and kits for performing immunoassay tests on a sample. The immunoassay devices may be used in conjunction with diagnostic reader systems for obtaining a sensitive read-out of the immunoassay results. The immunoassay devices may be especially suited for the detection of at least a first analyte and a second analyte in a sample. The immunoassay devices and methods may utilize a competitive binding-like assay and a sandwich binding assay to detect analytes in a sample.
    Type: Application
    Filed: January 30, 2020
    Publication date: September 24, 2020
    Inventors: Mengchun Qiu, Xiaodi Sun, Jijun Lin, Bin Miao, Xing Chang, Zheng Yang
  • Publication number: 20200295157
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20200291122
    Abstract: Provided herein are methods for treating cancer, comprising administering to a subject having cancer a therapeutically effective amount of an anti-GITR antibody alone or together with an anti-PD-1 or anti-PD-L1 antibody.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 17, 2020
    Inventors: Suba KRISHNAN, Penny E. PHILLIPS, Zheng YANG, Haiqing WANG
  • Publication number: 20200268026
    Abstract: A solubilized steviol glycoside composition including one or more steviol glycosides and one or more steviol glycoside solubility enhancers can be used as a sweetener composition to sweeten other compositions (sweetenable compositions) such as foods, beverages, medicines, oral hygiene compositions, pharmaceuticals, nutraceuticals, and the like.
    Type: Application
    Filed: October 8, 2018
    Publication date: August 27, 2020
    Applicant: CARGILL, INCORPORATED
    Inventors: Anil Bhagwan KHARE, Zheng Yang
  • Patent number: 10750111
    Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line coupled to a column of pixels is separated in to a plurality of electrically portions that are coupled to corresponding portions of rows of the pixel array. A first switching circuit of a readout circuit is coupled to the bit line. A first switching circuit is configured to couple a bit line current source to the bit line to provide a DC current coupled to flow through the bit line and through the first switching circuit during a readout operation of a pixel coupled to the bit line. A second switching circuit is configured to couple and ADC to the bit line during the readout operation of the pixel. Substantially none of the DC current provided by the bit line current source flows through the second switching circuit during the readout operation of the pixel.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 18, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hiroaki Ebihara, Rui Wang, Zheng Yang, Eiichi Funatsu
  • Publication number: 20200260031
    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Hiroaki Ebihara, Zheng Yang, Rui Wang, Teijun Dai
  • Publication number: 20200251390
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Shahaji B. More, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 10734524
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200243683
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 10698733
    Abstract: An execution platform comprising a workflow engine and an application engine is provided. A workflow definition associated with an application is received. The workflow definition is used to run an application workflow to perform an action with respect to the application, at least in part by causing an executable binary to be run by the application engine.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 30, 2020
    Assignee: Intuit Inc.
    Inventors: Edward K. Lee, Hong Wang, Ying Xie, Zheng Yang
  • Publication number: 20200200528
    Abstract: A measuring program compiling device and a measuring program compiling method thereof are provided. The method includes analyzing a first measuring program to obtain a plurality of first measuring parameters corresponding to the first measuring program, and converting the first measuring parameters into a plurality of second measuring parameters corresponding to a plurality of planning operations; generating a plurality of standardized measuring parameters according to the second measuring parameters and a plurality of computer aided design (CAD) image parameters; receiving a plurality of parameter input operations corresponding to the planning operations to update the second measuring parameters; generating a standardized measuring program corresponding to a CAD file according to the standardized measuring parameters; and converting the standardized measuring program into a target measuring program executed on a target measuring device according to specification data of the target measuring device.
    Type: Application
    Filed: April 17, 2019
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Kai-Ming Pan, Ta-Jen Peng, Yen-Cheng Chen, Qi-Zheng Yang, Chen-Yu Kai
  • Publication number: 20200182542
    Abstract: The present disclosure provides a supercritical compressed air energy storage system. The supercritical compressed air energy storage system includes a supercritical liquefaction subsystem, an evaporation and expansion subsystem, a staged cryogenic storage subsystem, a heat storage and heat exchange subsystem, and a cryogenic energy compensation subsystem, the staged cryogenic storage subsystem being used for implementing the staged storage and release of cryogenic energy, improving efficiency of recovering cryogenic energy during energy release and energy storage, and thereby improving cycle efficiency of the system. The present disclosure does not need to provide any inputs of additional cryogenic energy and heat energy input externally, and has the advantages of high cycle efficiency, low cost, independent operation, environmental friendliness, and no limitation on terrain conditions, and it is suitable for large-scale commercial applications.
    Type: Application
    Filed: June 1, 2017
    Publication date: June 11, 2020
    Inventors: Xipeng LIN, Liang WANG, Haisheng CHEN, Ningning XIE, Zheng YANG