Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Abstract: A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.

Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: An array substrate and a display panel. The array substrate includes: a substrate; a patterned shielding layer, having a fixed potential, arranged on one side of the substrate, and includes multiple shielding units connected to each other; and a driving circuit layer, arranged on one side of the shielding layer away from the substrate and comprising multiple driving transistors. An orthographic projection of each of the plurality of driving transistors projected on the shielding layer at least partially covers a corresponding one of the shielding units.

Abstract: A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

Abstract: A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data.

Abstract: A display panel and a display device. The display panel includes a first area and a second area, and a plurality of first pixel rows and a plurality of second pixel rows, each of the first pixel row and the second pixel row includes a plurality of pixels. The number of the pixels of each first pixel row is greater than the number of the pixels of each second pixel row. The pixels in the first pixel row are display pixels, and the plurality of pixels in the second pixel row are display pixels and virtual pixels. The display pixel includes a display pixel circuit, the virtual pixel includes a virtual pixel circuit, and the virtual pixel circuit includes a compensation unit.

Abstract: A shift register and a display panel. The shift register includes an output adjustment module, a trigger write module, and a node adjustment module. A first terminal of the output adjustment module inputs a first clock signal. A second terminal of the output adjustment module inputs a first power signal. The output adjustment module is configured to adjust the shift register to output the first clock signal or the first power signal according to the signal on a first control node and the signal on a second control node of the output adjustment module. The trigger write module is configured to write a trigger signal to the second control node according to the clock signal of the control terminal of the trigger write module. The node adjustment module is configured to adjust the signal on the first control node.

Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

Abstract: A thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate includes a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm.

Abstract: A display panel and a display device. The display panel includes a first area and a second area, and a plurality of first pixel rows and a plurality of second pixel rows, each of the first pixel row and the second pixel row includes a plurality of pixels. The number of the pixels of each first pixel row is greater than the number of the pixels of each second pixel row. The pixels in the first pixel row are display pixels, and the plurality of pixels in the second pixel row are display pixels and virtual pixels. The display pixel includes a display pixel circuit, the virtual pixel includes a virtual pixel circuit, and the virtual pixel circuit includes a compensation unit.

Abstract: The present application discloses an array substrate, a display panel, and a display apparatus. The array substrate includes a hole-punching area, a wiring area at least partially surrounding the hole-punching area and a wire-wrapping area between the hole-punching area and the wiring area, the array substrate includes: a substrate and a first wiring layer arranged on the substrate; a shielding assembly at least including a first shielding layer arranged on a side of the first wiring layer, the side of the first wiring layer being away from the substrate, and the first shielding layer being insulated from the first signal wires in the first wiring layer, the first shielding layer being electrically connected to a first fixed potential terminal, wherein an orthographic projection of the first shielding layer on the substrate covers an orthographic projection of the first wire-wrapping segment of the first signal wire on the substrate.

Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

Abstract: A display panel includes a substrate. The substrate includes a display area, a bonding area disposed on one side of the display area and a fan-out area disposed between the bonding area and the display area. The fan-out area includes at least two metal layers, a first planarization layer and a first interconnection line layer which are stacked on a surface of the substrate.

Abstract: A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.

Abstract: There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

Abstract: The present disclosure relates to a pixel circuit, a driving method of a pixel circuit, and a display apparatus. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor and an organic light-emitting diode. A control terminal of the fourth transistor is configured to input a first scanning signal. A first electrode of the fourth transistor is connected to a second electrode of the third transistor, a control terminal of the first transistor and a terminal of the first capacitor. Another terminal of the first capacitor is connected to a second electrode of the second transistor, a second electrode of the fifth transistor and a first electrode of the first transistor.

Abstract: An online system guarantees achievement of an impression goal and a reach goal associated with a set of content items received from a content-providing user of the online system within a period of time associated with the goals. To ensure that the goals are achieved within the period of time, the online system may adjust values of filters associated with the set of content items that control a number of impression opportunities for which the set of content items will be eligible for presentation to users of the online system. The online system may compute a normalized ratio throughout the period of time associated with the goals based on the goals and the progress made by the online system towards achieving the goals. Based on the normalized ratio, the online system may track the performance of the content items and adjust the values of the filters.

Abstract: The present disclosure provides a pixel circuit, a method for driving a pixel circuit, a display panel, and a display apparatus. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a capacitor, and a light-emitting diode. In the above pixel circuit, the first light emitting control signal and the second light emitting control signal are provided to respectively initialize the first polar plate and the second polar plate of the capacitor, to ensure the same initial state of the pixel circuits.

Abstract: The present application provides a display panel and a driving method of a pixel circuit. The display panel includes a scan driver, a light-emitting control driver, a data driver, a plurality of pixel circuits, and a plurality of pixels each corresponding to one of the pixel circuits. Each of the pixel circuits includes a first transistor to a seventh transistor, a capacitor and an organic light-emitting diode. A control terminal of the fourth transistor is configured to input a first scanning signal; and a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a control terminal of the first transistor and a terminal of the capacitor. Another terminal of the capacitor is connected to a first electrode of a fifth transistor. A second electrode of the fourth transistor is configured to input a first reference voltage.