Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract: An improved structure and method for forming isolation between two adjacent field effect transistors is disclosed. A large substrate cavity is formed between gates of the two adjacent transistors. The substrate cavity is filled with an epitaxial material such as epitaxial silicon, silicon germanium, or III-V compound semiconductor to form an epitaxial region. A cavity is then formed in the epitaxial material, dividing the epitaxial region into two epitaxial regions that serve as source-drain regions.

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.