Patents by Inventor Zhenyu Hu
Zhenyu Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10475890Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: GrantFiled: October 9, 2017Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor, Erik Geiss, Jerome Ciavatti, Jae Gon Lee
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Publication number: 20190341448Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.Type: ApplicationFiled: May 2, 2018Publication date: November 7, 2019Inventors: Emilie M.S. Bourjot, Julien Frougier, Yi Qi, Ruilong Xie, Hui Zang, Hsien-Ching Lo, Zhenyu Hu
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Patent number: 10431665Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.Type: GrantFiled: January 19, 2018Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
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Patent number: 10396206Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.Type: GrantFiled: July 7, 2017Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ashish Kumar Jha, Haiting Wang, Wei Hong, Wei Zhao, Tae Jeong Lee, Zhenyu Hu
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Patent number: 10355104Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.Type: GrantFiled: October 27, 2017Date of Patent: July 16, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, Jr., Shesh Mani Pandey
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Patent number: 10326002Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.Type: GrantFiled: June 11, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hui Zang, Ruilong Xie, Scott Beasor, Zhenyu Hu
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Publication number: 20190131432Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Inventors: Yi Qi, Sang Woo Lim, Kyung-Bum Koo, Alina Vinslava, Pei Zhao, Zhenyu Hu, Hsien-Ching Lo, Joseph F. Shepard, JR., Shesh Mani Pandey
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Publication number: 20190109197Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: ApplicationFiled: October 9, 2017Publication date: April 11, 2019Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
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Publication number: 20190035633Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.Type: ApplicationFiled: July 31, 2017Publication date: January 31, 2019Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan
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Patent number: 10192746Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.Type: GrantFiled: July 31, 2017Date of Patent: January 29, 2019Assignee: Globalfoundries Inc.Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan
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Publication number: 20190013245Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Ashish Kumar JHA, Haiting WANG, Wei HONG, Wei ZHAO, Tae Jeong LEE, Zhenyu HU
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Publication number: 20180330995Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Xinyuan DOU, Hong YU, Zhenyu HU, Xing ZHANG
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Publication number: 20180323191Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.Type: ApplicationFiled: January 17, 2018Publication date: November 8, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: HAITING WANG, WEI ZHAO, HONG YU, XUSHENG WU, HUI ZANG, ZHENYU HU
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Patent number: 10121788Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.Type: GrantFiled: January 17, 2018Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Haiting Wang, Wei Zhao, Hong Yu, Xusheng Wu, Hui Zang, Zhenyu Hu
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Patent number: 10090382Abstract: The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.Type: GrantFiled: November 14, 2017Date of Patent: October 2, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Hong Yu, Xinyuan Dou, Hui Zhan, Zhenyu Hu
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Publication number: 20180277440Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.Type: ApplicationFiled: March 23, 2017Publication date: September 27, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Hong YU, Zhenyu HU, Haiting WANG
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Patent number: 10083873Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures with uniform gate heights and methods of manufacture. The structure includes: short channel devices in a first area of an integrated circuit die; and long channel devices in a second area of the integrated circuit die. The long channel devices have a same gate height as the short channel devices.Type: GrantFiled: June 5, 2017Date of Patent: September 25, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Xing Zhang, Xinyuan Dou, Hong Yu, Zhenyu Hu
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Patent number: 10083874Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.Type: GrantFiled: March 23, 2017Date of Patent: September 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Hong Yu, Zhenyu Hu, Haiting Wang
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Patent number: 10056486Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.Type: GrantFiled: March 24, 2016Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shesh Mani Pandey, Pei Zhao, Zhenyu Hu
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Patent number: 10043713Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.Type: GrantFiled: May 10, 2017Date of Patent: August 7, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Xinyuan Dou, Hong Yu, Zhenyu Hu, Xing Zhang