Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Embodiments of the current invention describe a method of plating platinum selectively on a copper film using a self-initiated electroless process. In particular, platinum films are plated onto very thin copper films having a thickness of less than 300 angstroms. The electroless plating solution and the resulting structure are also described. This process has applications in the semiconductor processing of logic devices, memory devices, and photovoltaic devices.

Abstract: Methods for improving selective deposition of a capping layer on a patterned substrate are presented, the method including: receiving the patterned substrate, the patterned substrate including a conductive region and a dielectric region; forming a molecular masking layer (MML) on the dielectric region; preparing an electroless (ELESS) plating bath, where the ELESS plating bath includes: a cobalt (Co) ion source: a complexing agent: a buffer: a tungsten (W) ion source: and a reducing agent; and reacting the patterned substrate with the ELESS plating bath for an ELESS period at an ELESS temperature and an ELESS pH so that the capping layer is selectively formed on the conductive region. In some embodiments, methods further include a pH adjuster for adjusting the ELESS pH to a range of approximately 9.0 pH to 9.2 pH. In some embodiments, the pH adjuster is tetramethylammonium hydroxide (TMAH). In some embodiments, the MML is hydrophilic.

Abstract: Method for monitoring and controlling a combinatorial process are presenting including: receiving a substrate; executing the combinatorial process, wherein the combinatorial process includes an in-line chemical preparation; analyzing the in-line chemical preparation for conformance with a corresponding in-line chemical preparation parameter using an in-line chemical analysis; and if the in-line chemical preparation is out of conformance with the corresponding in-line chemical preparation parameter, adjusting the in-line chemical preparation to conform with the corresponding in-line chemical preparation parameter utilizing a replenishing chemical preparation. In some embodiments, methods further include: performing a post-chemical mechanical planarization (CMP) clean before executing the combinatorial process, wherein the combinatorial process is a pre-clean; and depositing a capping layer after the pre-clean.

Abstract: Embodiments of the invention teach a method for depositing a copper seed layer to a substrate surface, generally to a barrier layer. The method includes placing the substrate surface into a copper solution, wherein the copper solution includes complexed copper ions. A current or bias is applied across the substrate surface and the complexed copper ions are reduced to deposit the copper seed layer onto the barrier layer.

Abstract: Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable adhesion properties to a barrier and seed layers formed on a semiconductor substrate and demonstrate enhanced electromigration and stress migration results in the fabricated devices formed on the substrate.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: The present invention teaches a method for depositing a copper seed layer onto a substrate surface, generally onto a barrier layer. The barrier layer may include a refractory metal and/or a group 8, 9 or 10 metal. The method includes cathodically pre-treating the substrate in an acid-containing solution. The substrate is then placed into a copper solution (pH?7.0) that includes complexed copper ions and a current or bias is applied across the substrate surface. The complexed copper ions are reduced to deposit a copper seed layer onto the barrier layer. In one aspect, a complex alkaline bath is then used to electrochemically plate a gapfill layer on the substrate surface, followed by overfill in the same bath. In another aspect, an acidic bath ECP gapfill process and overfill process follow the alkaline seed layer process.

Abstract: Generally, the process includes depositing a barrier layer and seed layer on a feature formed in a dielectric layer, performing a grafting process, initiating a copper layer and then filing the feature by use of a bulk copper fill process. Copper features formed according to aspects described herein have desirable adhesion properties to a barrier and seed layers formed on a semiconductor substrate and demonstrate enhanced electromigration and stress migration results in the fabricated devices formed on the substrate.

Abstract: A method is disclosed for depositing a copper seed layer onto a substrate surface, generally onto a barrier layer that is an alloy of a group VIII metal and a refractory metal. In one aspect, the alloy consists of at least 50% ruthenium and the balance a copper diffusion barrier material. A copper layer is electroplated on the alloy directly. In one aspect, the surface of the barrier layer is conditioned prior to plating to improve adhesion and reduce the critical current density for plating on the barrier layer. The conditioning may include cathodic pre-treatment or a plasma pre-treatment in a hydrogen or hydrogen/helium mixture. In one aspect, the substrate surface is immersed in an acidic plating bath and a nucleation waveform is applied to form a seed layer. In another aspect, the substrate is immersed in a neutral or alkaline copper solution that includes complexed copper ions.

Abstract: Embodiments of the invention generally include a method and intermediate plating solution for plating metal onto a substrate surface. The method generally includes filling the features and/or growing a film layer on the field areas by plating a metal from a first solution on a seed layer under an applied first current, wherein the first solution includes an acid in an amount sufficient to provide a first solution pH of about 6 or less, copper ions, and at least one suppressor. The method may further include substantially filling features by plating metal ions from a second solution onto the substrate under an applied second current to form a metal layer, wherein the second solution includes an acid in an amount sufficient to provide a second solution pH of from about 0.

Abstract: A method and apparatus for analyzing plating solutions. The apparatus generally includes a plating cell, a reference electrolyte input, one or more external additive pumps, and a process controller. In one embodiment, the plating cell includes a cavity therein having a larger volumetric portion adjacent a smaller volumetric portion adapted to hold one or more solutions therein. The plating cell also includes a base disposed adjacent the bottom of the plating cell and adapted to receive and mix one or more test solutions as part of the plating solution analysis. In one configuration, the base includes electrical ports adapted to connect stimulation signals to a working electrode, counter electrode, and reference electrode disposed within the cell. The base also includes a thermal sensor in thermal contact with test solutions contained within the vessel.

Abstract: A method and apparatus for analyzing plating solutions. The apparatus generally includes a plating cell, a reference electrolyte input, one or more external additive pumps, and a process controller. In one embodiment, the plating cell includes a cavity therein having a larger volumetric portion adjacent a smaller volumetric portion adapted to hold one or more solutions therein. The plating cell also includes a base disposed adjacent the bottom of the plating cell and adapted to receive and mix one or more test solutions as part of the plating solution analysis. In one configuration, the base includes electrical ports adapted to connect stimulation signals to a working electrode, counter electrode, and reference electrode disposed within the cell. The base also includes a thermal sensor in thermal contact with test solutions contained within the vessel.

Abstract: Embodiments of a method of barrier layer surface treatment to enable direct copper plating without copper seed layer. In one embodiment, a method of plating copper on a substrate with a group VIII metal layer on top comprises pre-treating the substrate surface by removing a group VIII metal surface oxide layer and/or surface contaminants and plating copper on the pre-treated group VIII metal surface.

Abstract: Embodiments of a method of copper plating a substrate surface with a group VIII metal layer have been described. In one embodiment, a method of plating copper on a substrate surface with a group VIII metal layer comprises pre-treating the substrate surface by removing a group VIII metal surface oxide layer and/or surface contaminants and plating the substrate in a copper plating solution comprising about 50 g/l to about 300 g/l of sulfuric acid at an initial plating current higher than the critical current density to deposit a continuous copper layer on the substrate surface. The Pre-treating the substrate can be accomplished by annealing the substrate in an environment with a hydrogen-containing gas environment and/or a non-reactive gas(es) to Ru, by a cathodic treatment in an acid-containing bath, or by immersing the substrate in an acid-containing bath.

Abstract: A method for electrolytically repairing a copper seed layer. The method includes positioning the seed layer in fluid communication with a low conductivity seed layer repair solution, wherein the low conductivity seed layer repair solution includes a copper concentration of less than about 20 g/l, a pH of less than about 4, a chlorine ion concentration of between about 20 ppm and about 100 ppm, and an additive organic surfactant configured to suppress a copper deposition rate in the concentration range of 200 ppm to 2000 ppm. The method further includes applying a seed layer repair bias configured to generate a current density of less than about 5 mA/cm2 across the seed layer and cleaning the repaired seed layer in pure water containing less than 1 ppm chloride ions.