Patents by Inventor Zhijian Yang

Zhijian Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190274638
    Abstract: The present disclosure provides an electronic device and an alarm control method. The electronic device includes: a detecting component, configured to obtain a physiological feature parameter of a user; a first input component, configured to receive verification information inputted by the user; and a first processing component, configured to receive the inputted verification information via the first input component when determining that the physiological feature parameter obtained by the detecting component satisfies a presupposed condition, perform a normal operating mode of the electronic device when determining that the verification information is first preset verification information, and perform an alarm operation when determining that the verification information is second preset verification information. The alarm operation at least includes transmitting first prestored information to a first object.
    Type: Application
    Filed: October 16, 2018
    Publication date: September 12, 2019
    Inventors: Chunmei YANG, Hui CHEN, Qiaoni WANG, Xingming CHEN, Zhijian CHEN, Xin XIE, Ming LI, Xinyu ZHANG
  • Publication number: 20190267568
    Abstract: The present disclosure relates to the field of display technology, in particular to a display panel, a manufacturing method thereof, and a display device. The display panel includes a display substrate and an encapsulation layer for encapsulating the display substrate. The encapsulation layer includes at least one inorganic composite film layer, and each inorganic composite film layer includes an inorganic matrix and an inorganic filler. The inorganic matrix includes a plurality of grains spaced apart by gaps, and the inorganic filler is capable of enclosing each grain and being filled in a gap between every two adjacent grains.
    Type: Application
    Filed: December 17, 2018
    Publication date: August 29, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianfeng LIU, Ni YANG, Zhongfei DONG, Zhijian QI, Yunze LI, Xin LIU
  • Publication number: 20190238691
    Abstract: The present disclosure discloses an information exhibiting device and method. The information exhibiting device includes a display component and an information acquisition component that are connected to each other. The information acquisition component is configured to acquire target information. The display component is provided with an information exhibiting interface which may be displayed on the display component after the information exhibiting device is powered on. The information exhibiting interface includes a target information exhibiting region. The display component is configured to exhibit the target information, which is acquired by the information acquisition component, in the target information display region. The information exhibiting device provided by an embodiment of the present disclosure may guarantee that memo information has low probability of getting lost. Thus, a user may be effectively reminded.
    Type: Application
    Filed: August 30, 2018
    Publication date: August 1, 2019
    Inventors: Qiaoni Wang, Yabin Lin, Hui Chen, Chunmei Yang, Zhijian Chen, Xingming Chen, Xinyu Zhang
  • Publication number: 20190239363
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Application
    Filed: April 11, 2019
    Publication date: August 1, 2019
    Applicant: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 10361317
    Abstract: A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: July 23, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Keke Gu, Ni Yang, Wei Hu, Zhongping Gou, Xin Liu, Zhijian Qi, Yusong Hou, Shuai Chen
  • Patent number: 10321581
    Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: June 11, 2019
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
  • Patent number: 9985615
    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
  • Patent number: 9768110
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9721854
    Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20170141771
    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
  • Patent number: 9391014
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20160190005
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9337334
    Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang
  • Patent number: 9331012
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: May 3, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20160071742
    Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9281236
    Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9217769
    Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Hailing Wang, Zhijian Yang
  • Publication number: 20150348899
    Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9190360
    Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
  • Publication number: 20150303313
    Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang