Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.

Abstract: An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Abstract: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

Abstract: Sunless tanning compositions with nucleophile functionalized sulfonic acids are described. The compositions are stable and result in excellent tanning results when sunless tanning agents like 1,3-dihydroxy-2-propanone are used.

Abstract: A method for nondestructive laser lift-off of GaN from sapphire substrates utilizing a solid-state laser is disclosed in the present invention, wherein, a solid-state laser is used as the laser source, and a small laser-spot with a circumference of 3 to 1000 micrometers and a distance of two farthest corners or a longest diameter of no more than 400 micrometers is used for laser scanning point-by-point and line-by-line, wherein the energy in the small laser-spot is distributed such that the energy in the center of the laser-spot is the strongest and is gradually reduced toward the periphery. According to the present invention, a nondestructive laser lift-off with a small laser-spot is achieved, and a scanning mode of the laser lift-off is improved, thereby a lift-off method without the need of aiming is achieved.

Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×le×VCER)], VCER=VBER+VCBR, and le=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the tr

Abstract: A method of recovering gain in a bipolar transistor includes: providing a bipolar transistor including an emitter, a collector, and a base disposed between junctions at the emitter and the collector; reverse biasing the junction disposed between the emitter and the base with an operational voltage and for an operational time period, so that a current gain ? of the transistor is degraded; idling the transistor, and generating a repair current Ibr into the base, while forward biasing the junction disposed between the emitter and the base with a first repair voltage (VEBR), and while at least partly simultaneously reverse biasing the junction disposed between the collector and the base with a second repair voltage (VCBR), for a repair time period (TR), so that the gain is at least party recovered; wherein VEBR, VCBR and TR have the proportional relationship: TR ? (??)2×exp [1/(Tam+Rth×1e×VCER], VCER=VBER+VCBR, and 1e=?×Ibr, ? is the normal current gain of the transistor, ?? is the target recovery gain of the tra

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: The present invention relates to highly conjugated proteins and methods for making such proteins. In particular, the present invention relates to methods for linking additional sites to a protein for conjugation with activated polyethylene glycol (PEG) linkers, without denaturing the protein. The invention also relates to highly conjugated proteins with decreased immunogenicity and increased circulating half-life.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.