Patents by Inventor Zhijian Yang
Zhijian Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9985615Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.Type: GrantFiled: February 1, 2017Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
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Patent number: 9768110Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: March 4, 2016Date of Patent: September 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9721854Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.Type: GrantFiled: December 5, 2012Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20170141771Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.Type: ApplicationFiled: February 1, 2017Publication date: May 18, 2017Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
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Patent number: 9391014Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: August 13, 2015Date of Patent: July 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20160190005Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9337334Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.Type: GrantFiled: April 21, 2014Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang
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Patent number: 9331012Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: GrantFiled: March 8, 2012Date of Patent: May 3, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20160071742Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: ApplicationFiled: November 16, 2015Publication date: March 10, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9281236Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: GrantFiled: May 21, 2015Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9217769Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.Type: GrantFiled: October 9, 2012Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Hailing Wang, Zhijian Yang
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Publication number: 20150348899Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.Type: ApplicationFiled: August 13, 2015Publication date: December 3, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9190360Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: GrantFiled: February 17, 2014Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150303313Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.Type: ApplicationFiled: April 21, 2014Publication date: October 22, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hari V. Mallela, Edward J. Nowak, Yunsheng Song, Reinaldo A. Vega, Keith Kwong Hon Wong, Zhijian Yang
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Publication number: 20150255326Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9117824Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: GrantFiled: September 20, 2013Date of Patent: August 25, 2015Assignee: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150235964Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9077319Abstract: A clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, whereby the phase detector generates a phase signal based on a phase difference between the first and the second clock signal. A first integrator is coupled to the phase detector, receives the phase signal, and generates an integrated phase signal. A second integrator receives the first clock signal and generates an integrated first clock signal. A comparator is coupled to the first and the second integrator, whereby the comparator receives the integrated phase signal and the integrated first clock signal. The comparator may then generate a control signal that detects a change between the phase difference of the first and the second clock signal and an optimized phase difference based on an amplitude comparison between the integrated phase signal and the integrated first clock signal.Type: GrantFiled: January 16, 2014Date of Patent: July 7, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Jong-ru Guo, Trushil N. Shah, Ping-Chuan Wang, Zhijian Yang
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Patent number: 9059204Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.Type: GrantFiled: April 28, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Kai D. Feng, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Zhijian Yang
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Publication number: 20150084193Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Applicant: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian Yang