Patents by Inventor Zhiqiang Wu

Zhiqiang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRANSISTOR DESIGN
    Publication number: 20160035832
    Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Wen-Yuan Chen, Tsung-Hsing Yu, Ken-Ichi Goto, Zhiqiang Wu
  • Fin Structure of Semiconductor Device
    Publication number: 20160035827
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Carlos H. Diaz, Chih-Hao Wang, Kuo-Cheng Ching, Zhiqiang Wu
  • FinFETs with gradient germanium-containing channels
    Patent number: 9245882
    Abstract: A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhiqiang Wu, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Transistor having replacement gate and epitaxially grown replacement channel region
    Patent number: 9236445
    Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Ken-Ichi Goto, Zhiqiang Wu
  • MOSFET WITH SELECTIVE DOPANT DEACTIVATION UNDERNEATH GATE
    Publication number: 20160005817
    Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Wei-Hao WU, Ken-Ichi GOTO, Zhiqiang WU, Yuan-Chen SUN
  • Source and drain dislocation fabrication in FinFETs
    Patent number: 9230828
    Abstract: A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
  • Structure and Method for SRAM FinFET Device
    Publication number: 20150380410
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu, Carlos H. Diaz
  • Process design to improve transistor variations and performance
    Patent number: 9224814
    Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • Structure and method for SRAM FinFET device
    Patent number: 9224736
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu, Carlos H. Diaz
  • Fin structure of semiconductor device
    Patent number: 9219116
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz
  • Semiconductor device with a buried stressor
    Patent number: 9219152
    Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Jeffrey Junhao Xu, Chih-Hao Chang, Wen-Hsing Hsieh
  • HINDERED PHENOL COMPOUND, PREPARATION THEREOF AND USE THEREOF AS AN ANTIOXIDANT
    Publication number: 20150353858
    Abstract: This invention relates to a novel hindered phenol compound of Formula (I) (wherein the groups R and R? are as defined in the specification), preparation thereof and use thereof as an antioxidant. By using the hindered phenol compound of this invention as an antioxidant, it is possible to produce a lubricant oil composition exhibiting excellent oxidation resistance at elevated temperatures.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Shuo SU, Jun LONG, Qinghua DUAN, Han ZHOU, Zhiqiang WU, Xinhua LI, Yi ZHAO, Xiaoguang ZHAO
  • Structure and method for FinFET device
    Patent number: 9209303
    Abstract: The present disclosure provides a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first region, a second region and a third region. The first region includes a first fin structure, a first high-k (HK)/metal gate (MG) stack wrapping over an upper portion of the first fin structure and a first source/drain features, separated by the first HK/MG stack, over the recessed first fin structure. The second region includes a second fin structure, the first source/drain features over a portion of the recessed second fin structure. The third region includes a dummy gate stack over the second fin structure and the two first regions are separated by the second region, or by the third region.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Method and structure for FinFET device
    Patent number: 9209185
    Abstract: The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Buried SiGe oxide FinFET scheme for device enhancement
    Patent number: 9202917
    Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Gwan Sin Chang
  • Intelligent Unmasking in an In-Memory Database
    Publication number: 20150331911
    Abstract: Database data is unmasked in order to facilitate its efficient handling by a database engine. In response to a request for data of a masked table including a masked element, an engine identifies a mask interval, and then performs a first join with unmasked elements sharing a common key. The table resulting from this first join is then grouped according to a highest level location of the mask. A second join is then performed between the results of this grouping and the mask interval, to produce a corresponding unmasked table including a plurality of unmasked elements corresponding to the masked element. Unmasking according to embodiments may be particularly useful in leveraging processing power of an in-memory database engine, allowing it to efficiently perform batch processing of requests for masked data received from software of an overlying application layer.
    Type: Application
    Filed: May 13, 2014
    Publication date: November 19, 2015
    Applicant: SAP AG
    Inventor: ZHIQIANG WU
  • Transistor design
    Patent number: 9184234
    Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Yuan Chen, Tsung-Hsing Yu, Ken-Ichi Goto, Zhiqiang Wu
  • Structure and method for FinFET device
    Patent number: 9178067
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Structure and Method for FinFET Device
    Publication number: 20150311207
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a plurality of first fin structures over a substrate. The first fin structure includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer, being at least partially surrounded by a semiconductor oxide feature. The device also includes a third semiconductor material layer disposed over the second semiconductor material layer and a second fin structures over the substrate and adjacent to one of the first fin structures. The second fin structure includes the first semiconductor material layer and the third semiconductor material layer disposed over the dielectric layer.
    Type: Application
    Filed: October 1, 2014
    Publication date: October 29, 2015
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • STRUCTURE AND METHOD FOR FINFET DEVICE
    Publication number: 20150311335
    Abstract: The present disclosure provides a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first region, a second region and a third region. The first region includes a first fin structure, a first high-k (HK)/metal gate (MG) stack wrapping over an upper portion of the first fin structure and a first source/drain features, separated by the first HK/MG stack, over the recessed first fin structure. The second region includes a second fin structure, the first source/drain features over a portion of the recessed second fin structure. The third region includes a dummy gate stack over the second fin structure and the two first regions are separated by the second region, or by the third region.
    Type: Application
    Filed: May 29, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu