Abstract: In an example, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, a semiconductor layer over the memory stack and electrically connected to the channel structure, and a source contact over the memory stack and electrically connected to the semiconductor layer. The source contact and the memory stack are disposed on opposite sides of the semiconductor layer.

Abstract: A three-dimensional (3D) memory device includes a first region and a second region arranged along a first direction, a stack structure including interleaved conductive layers and dielectric layers along a second direction perpendicular to the first direction, a semiconductor layer located on a side of the stack structure along the second direction, a source contact structure at a first side of the semiconductor layer opposite to the stack structure, wherein the source contact structure is in contact with the semiconductor layer, a peripheral circuit at a second side of the semiconductor layer opposite to the first side of the semiconductor layer, and a supporting structure located in the second region and extending through the semiconductor layer along the second direction, wherein a material of the supporting structure is different from a material of the semiconductor layer.

Abstract: A three-dimensional (3D) memory device includes a memory stack including a memory block. The memory block includes a memory array structures and a staircase structure in a first lateral direction, and fingers in a second lateral direction perpendicular to the first lateral direction. The fingers include a first finger and a second finger. The 3D memory device also includes a source-select-gate (SSG) cut structure extending through a portion of the memory stack and between the first finger and the second finger. The staircase structure includes a first staircase connected to first memory cells in the first finger and a second staircase connected to second memory cells in the second finger.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

Abstract: A Lentinula edodes-derived saltiness enhancing peptide, a method for preparing the same and use thereof are provided herein, belonging to the technical field of active peptides. The Lentinula edodes-derived saltiness enhancing peptide is derived from an enzymolysis extract of a Lentinula edodes fruiting body by flavourzyme and shows a strong ability to enhance saltiness. Compared with the saltiness value of a 4.0 g/L NaCl solution, the Lentinula edodes-derived saltiness enhancing peptide could replace about 50% of NaCl, thus reducing salt without reducing saltiness. Moreover, the Lentinula edodes-derived saltiness enhancing peptide also has a high umami value and can be used in preparation of low-salt foods including low-salt and flavor-enhancing foods.

Abstract: A semiconductor structure comprises layers of transistors stacked in a vertical direction. Each layer of transistors comprises: a first array of transistors sharing a first common first-type terminal line; a second array of transistors sharing a second common first-type terminal line. The first array of transistors and the second array of transistors share a common second-type terminal line. The semiconductor structure further comprises a first common first-type terminal contact structure coupled with the first common first-type terminal line in a first first-type terminal contact region, a second common first-type terminal contact structure coupled with the second common first-type terminal line in a second first-type terminal contact region, and a common second-type terminal contact structure coupled with the common second-type terminal line in a common second-type terminal contact region.

Abstract: A three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and second memory array structures in a first lateral direction. The staircase structure includes a first staircase zone and a second staircase zone. The staircase structure includes a bridge structure connected with the first memory array structure and the second memory array structure, and the bridge structure includes a gate line slit structure extending along the first lateral direction. The bridge structure is between the first staircase zone and the second staircase zone in a second lateral direction perpendicular to the first lateral direction. The first staircase zone includes a plurality of stairs, and the second staircase zone includes a plurality of stairs. The first staircase zone includes a first pair of staircases. The first pair of staircases face each other in the first lateral direction and are at different depths.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: A semiconductor device includes a stack including word line layers and insulating layers that are alternatingly stacked, a first block including a first staircase positioned in the stack that extends between first array regions, a second block including a second staircase positioned in the stack that extends between second array regions, a connection region positioned in the stack, wherein the first array regions and the first staircase are positioned at a first side of the connection region, and the second array regions and the second staircase are positioned at a second side of the connection region, and a slit structure positioned in the connection region between the first staircase and the second staircase. The slit structure includes a dielectric material and divides the connection region into a first portion and a second portion.

Abstract: The present invention provides a curable composition, a curable adhesive film, and an adhesive tape. Specifically, the curable composition comprises, based on the total weight thereof as 100 wt %: 15-50 wt % of an ethylene-vinyl acetate copolymer; 10-40 wt % of polyvinyl butyral; and 20-60 wt % of an epoxy resin. The curable adhesive film according to the technical solution of the present invention has no tackiness at room temperature, which enables the curable adhesive film to have the ability to reposition even after being laminated on a substrate, making the curable adhesive film applicable to substrates with irregular shapes. Once initiated by UV radiation, the curable adhesive film is flowable and tacky at elevated temperatures. The cured adhesive has good bonding strength at high temperatures. The curable adhesive film features high bond strength and low odor, and can be used for void filling, especially for side panel bonding of electric vehicle battery modules in the electric vehicle (EV) market.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a semiconductor layer, a first stack structure, a second stack structure, a gate line isolation structure, and a first dielectric layer. The first stack structure includes a plurality of first insulating layers and a plurality of gate line layers disposed alternatively. The second stack structure is disposed on a side of the first stack structure away from the semiconductor layer and includes a select gate line layer. The gate line isolation structure penetrates through the first stack structure and the second stack structure in a direction perpendicular to the semiconductor layer. The first dielectric layer is disposed on a side of the second stack structure away from the semiconductor layer, contacts the gate line isolation structure, and covers at least a part of a surface of the gate line isolation structure away from the semiconductor layer.

Abstract: A semiconductor device includes a stack including gate layers and insulating layers alternately stacked along a first direction, channel structures located in an array region of the stack, a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction, a second staircase located at a second section in the connection region of the stack, and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction. The intermediate staircase includes intermediate group stair steps ascending in the second direction. The intermediate staircase has a first sidewall and a second sidewall in the second direction. The second sidewall is closer to the second staircase than the first sidewall. The second sidewall is parallel to the first direction.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stack structure including conductor layers and dielectric layers stacked alternately along a first direction. The semiconductor device may include at least one semiconductor structure penetrating through the stack structure. The semiconductor structure may include a capacitor structure, a first transistor structure, and a second transistor structure extending in the stack structure along the first direction. The second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure may be arranged and connected sequentially along the first direction.

Abstract: A semiconductor structure and a manufacturing method thereof, and a memory system are provided. The semiconductor structure may include a stack structure including a first region, a second region and a boundary region between the first region and the second region. The stack structure includes gate layers and insulation layers stacked alternately, and the gate layers include a first gate layer and a plurality of second gate layers on a side of the first gate layer. A first contact structure in the boundary region extends and connects to the first gate layer. A plurality of second contact structures in the second region extend and connect to the second gate layers of different layers respectively. A size of the first contact structure perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures perpendicular to the stacking direction.

Abstract: In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device may also include a plurality of landing structures each disposed on a respective conductive layer at a respective stair. Each of the landing structures comprises a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different from the first material.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked layer and a top select gate layer located on the stacked layer. The semiconductor device may include a gate-line structure extending through the top select gate layer and the stacked layer. A portion of the gate-line structure that extends through the top select gate layer may be a first isolation structure, and the first isolation structure may include a contact layer in contact with the top select gate layer. The semiconductor device may include a channel structure extending through the stacked layer and a first dielectric layer located on the top select gate layer, where the first dielectric layer and the contact layer comprise different insulating materials. The semiconductor device may include a channel local contact extending through the first dielectric layer and corresponding to the channel structure.