Abstract: A Lentinula edodes-derived saltiness enhancing peptide, a method for preparing the same and use thereof are provided herein, belonging to the technical field of active peptides. The Lentinula edodes-derived saltiness enhancing peptide is derived from an enzymolysis extract of a Lentinula edodes fruiting body by flavourzyme and shows a strong ability to enhance saltiness. Compared with the saltiness value of a 4.0 g/L NaCl solution, the Lentinula edodes-derived saltiness enhancing peptide could replace about 50% of NaCl, thus reducing salt without reducing saltiness. Moreover, the Lentinula edodes-derived saltiness enhancing peptide also has a high umami value and can be used in preparation of low-salt foods including low-salt and flavor-enhancing foods.

Abstract: A semiconductor structure comprises layers of transistors stacked in a vertical direction. Each layer of transistors comprises: a first array of transistors sharing a first common first-type terminal line; a second array of transistors sharing a second common first-type terminal line. The first array of transistors and the second array of transistors share a common second-type terminal line. The semiconductor structure further comprises a first common first-type terminal contact structure coupled with the first common first-type terminal line in a first first-type terminal contact region, a second common first-type terminal contact structure coupled with the second common first-type terminal line in a second first-type terminal contact region, and a common second-type terminal contact structure coupled with the common second-type terminal line in a common second-type terminal contact region.

Abstract: A three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and second memory array structures in a first lateral direction. The staircase structure includes a first staircase zone and a second staircase zone. The staircase structure includes a bridge structure connected with the first memory array structure and the second memory array structure, and the bridge structure includes a gate line slit structure extending along the first lateral direction. The bridge structure is between the first staircase zone and the second staircase zone in a second lateral direction perpendicular to the first lateral direction. The first staircase zone includes a plurality of stairs, and the second staircase zone includes a plurality of stairs. The first staircase zone includes a first pair of staircases. The first pair of staircases face each other in the first lateral direction and are at different depths.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: A semiconductor device includes a stack including word line layers and insulating layers that are alternatingly stacked, a first block including a first staircase positioned in the stack that extends between first array regions, a second block including a second staircase positioned in the stack that extends between second array regions, a connection region positioned in the stack, wherein the first array regions and the first staircase are positioned at a first side of the connection region, and the second array regions and the second staircase are positioned at a second side of the connection region, and a slit structure positioned in the connection region between the first staircase and the second staircase. The slit structure includes a dielectric material and divides the connection region into a first portion and a second portion.

Abstract: The present invention provides a curable composition, a curable adhesive film, and an adhesive tape. Specifically, the curable composition comprises, based on the total weight thereof as 100 wt %: 15-50 wt % of an ethylene-vinyl acetate copolymer; 10-40 wt % of polyvinyl butyral; and 20-60 wt % of an epoxy resin. The curable adhesive film according to the technical solution of the present invention has no tackiness at room temperature, which enables the curable adhesive film to have the ability to reposition even after being laminated on a substrate, making the curable adhesive film applicable to substrates with irregular shapes. Once initiated by UV radiation, the curable adhesive film is flowable and tacky at elevated temperatures. The cured adhesive has good bonding strength at high temperatures. The curable adhesive film features high bond strength and low odor, and can be used for void filling, especially for side panel bonding of electric vehicle battery modules in the electric vehicle (EV) market.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a semiconductor layer, a first stack structure, a second stack structure, a gate line isolation structure, and a first dielectric layer. The first stack structure includes a plurality of first insulating layers and a plurality of gate line layers disposed alternatively. The second stack structure is disposed on a side of the first stack structure away from the semiconductor layer and includes a select gate line layer. The gate line isolation structure penetrates through the first stack structure and the second stack structure in a direction perpendicular to the semiconductor layer. The first dielectric layer is disposed on a side of the second stack structure away from the semiconductor layer, contacts the gate line isolation structure, and covers at least a part of a surface of the gate line isolation structure away from the semiconductor layer.

Abstract: A semiconductor device includes a stack including gate layers and insulating layers alternately stacked along a first direction, channel structures located in an array region of the stack, a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction, a second staircase located at a second section in the connection region of the stack, and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction. The intermediate staircase includes intermediate group stair steps ascending in the second direction. The intermediate staircase has a first sidewall and a second sidewall in the second direction. The second sidewall is closer to the second staircase than the first sidewall. The second sidewall is parallel to the first direction.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stack structure including conductor layers and dielectric layers stacked alternately along a first direction. The semiconductor device may include at least one semiconductor structure penetrating through the stack structure. The semiconductor structure may include a capacitor structure, a first transistor structure, and a second transistor structure extending in the stack structure along the first direction. The second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure may be arranged and connected sequentially along the first direction.

Abstract: A semiconductor structure and a manufacturing method thereof, and a memory system are provided. The semiconductor structure may include a stack structure including a first region, a second region and a boundary region between the first region and the second region. The stack structure includes gate layers and insulation layers stacked alternately, and the gate layers include a first gate layer and a plurality of second gate layers on a side of the first gate layer. A first contact structure in the boundary region extends and connects to the first gate layer. A plurality of second contact structures in the second region extend and connect to the second gate layers of different layers respectively. A size of the first contact structure perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures perpendicular to the stacking direction.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device may also include a plurality of landing structures each disposed on a respective conductive layer at a respective stair. Each of the landing structures comprises a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different from the first material.

Abstract: In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked layer and a top select gate layer located on the stacked layer. The semiconductor device may include a gate-line structure extending through the top select gate layer and the stacked layer. A portion of the gate-line structure that extends through the top select gate layer may be a first isolation structure, and the first isolation structure may include a contact layer in contact with the top select gate layer. The semiconductor device may include a channel structure extending through the stacked layer and a first dielectric layer located on the top select gate layer, where the first dielectric layer and the contact layer comprise different insulating materials. The semiconductor device may include a channel local contact extending through the first dielectric layer and corresponding to the channel structure.

Abstract: According to one aspect of the present disclosure, a three-dimensional memory is provided. The three-dimensional memory may include a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps. The three-dimensional memory may include an etch stop layer disposed on the plurality of steps. The three-dimensional memory may include a protective layer covering the stack structure and the etch stop layer. The three-dimensional memory may include a plurality of connection pillars. Each of the connection pillars penetrates through the protective layer and the etch stop layer on a corresponding step and is connected with the gate layer of the corresponding step.

Abstract: The present disclosure provides a three-dimensional (3D) memory. The 3D memory may include a stack structure including gate layers and dielectric layers disposed alternately. The stack structure may include a step structure including a plurality of staircase structures disposed in a first direction and having different heights in a second direction. The 3D memory may include a plurality of first stops disposed in the first direction and located on the plurality of steps of at least one of the staircase structures, with each of the plurality of first stops disposed on the corresponding step of the plurality of steps. The 3D memory may include a protection layer covering the step structure and the first stops. The 3D memory may include a plurality of contact posts each extending through the protection layer and the first stop and being connected with the gate layer in the step corresponding to the first stop.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A semiconductor device includes a first bottom select gate (BSG) staircase, a first array region, a connection region, a second array region, and a second BSG staircase that are formed in a stack and disposed sequentially along a first direction of a substrate. The stack is formed of word line layers and insulating layers that are alternatingly disposed over the substrate. The first BSG staircase is formed in a first group of the word line layers, and the insulating layers and the second BSG staircase are formed in a second group of the word line layers and the insulating layers. The connection region includes a first top select gate (TSG) staircase positioned along the first array region, and a second TSG staircase positioned along the second array region. The first TSG staircase is formed in a third group of the word line layers, and the insulating layers and the second TSG staircase are formed in a fourth group of the word line layers and the insulating layers.