Patents by Inventor Zhong Zhang

Zhong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282673
    Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 22, 2024
    Inventors: Linchun WU, Kun ZHANG, Zhong ZHANG, Wenxi ZHOU, Zhiliang XIA
  • Patent number: 12068250
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: August 20, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20240274535
    Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs extending along a first lateral direction. The plurality of stairs include a stair including a conductor portion on a top surface of the stair. The conduction portion is connected to the memory array structure. Widths of conductor portions are different in a second lateral direction perpendicular to the first lateral direction.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Di WANG, Wenxi ZHOU, Zhiliang XIA, Zhong ZHANG
  • Patent number: 12063780
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: August 13, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
  • Patent number: 12058865
    Abstract: A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 6, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhong Zhang, Yuhui Han, Wenxi Zhou
  • Patent number: 12057372
    Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: August 6, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Linchun Wu, Kun Zhang, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 12052870
    Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: July 30, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhong Zhang, Wenyu Hua, Bo Huang, Zhiliang Xia
  • Publication number: 20240251558
    Abstract: In one aspect, a three-dimensional (3D) memory device includes a first core region, a second core region, and an isolation region between the first and second core regions along a first direction, a stack in the first and second core regions and including alternatingly stacked first dielectric layers and conductor layers, gate line slit structures extending through the stack along a second direction perpendicular to the first direction in the first and second core regions, top select gate (TSG) cut structures extending through a portion of the stack along the second direction, and a first isolation structure extending through the stack along the second direction in the isolation region and contacting with the gate line slit structures. The gate line slit structures and the TSG cut structures extend along the first direction. One of the TSG cut structures is between two of the gate line slit structures along a third direction perpendicular to the first direction and the second direction.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Inventors: Zhong ZHANG, Wenxi ZHOU, Zhiliang XIA
  • Patent number: 12046555
    Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: July 23, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 12048149
    Abstract: A 3D memory device includes a memory stack having a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of fingers in a second lateral. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone in the second lateral direction. The 3D memory device also includes a source-select-gate (SSG) cut structure extending in a SSG of the memory stack and between adjacent ones of the plurality of fingers of the memory block. The SSG cut structure is between a first finger and a second finger, the first finger includes a string. The staircase zone includes a staircase conductively connected to memory cells in the string in each of the first memory array structure and the second memory array structure through the bridge structure.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 23, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Zhong Zhang
  • Patent number: 12033944
    Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 12035525
    Abstract: A semiconductor device has a stack formed of word line layers and insulating layers that are alternatingly arranged over a substrate. A first connection region is arranged between first array regions in the stack, and a first separation structure positioned along first sides of the first connection region and the first array regions. The first separation structure extends through the stack into the substrate. A second separation structure is positioned along opposing second sides of the first connection region and the first array regions. The second separation structure includes array separation structures positioned along the second sides of the first array regions and a connection separation structure positioned along the second side of the first connection region. The connection separating structure is arranged between and aligned with the array separation structures, and further extends through the stack into the substrate.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 9, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Zhong Zhang
  • Patent number: 12033957
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: July 9, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhong Zhang, Di Wang, Wenxi Zhou
  • Publication number: 20240224526
    Abstract: A three-dimensional (3D) memory device includes a plurality of channel structures extending along a vertical direction, a first staircase structure including a plurality of division block structures arranged along a first direction on a side of the channel structures, and a top select gate staircase structure disposed between the channel structures and the first staircase structure in a second direction that is different from the first direction. At least one of the division block structures includes a plurality of staircases arranged along the second direction. At least one of the staircases includes a plurality of steps arranged along the first direction.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventors: Zhong ZHANG, Wenyu HUA, Zhiliang XIA
  • Patent number: 12008794
    Abstract: A method may include obtaining a video collected by a visual sensor, the video including a plurality of frames and detecting one or more objects from the video in at least a portion of the plurality of frames. The method may also include determining a first detection result associated with the one or more objects with a trained self-learning model. The method may further include selecting a target moving object of interest from the one or more objects at least in part based on the first detection result. The trained self-learning model may be provided based on a plurality of training samples collected by the visual sensor.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: June 11, 2024
    Assignee: SHANGHAI TRUTHVISION INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Zhong Zhang
  • Patent number: 12002757
    Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: June 4, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Di Wang, Wenxi Zhou, Zhiliang Xia, Zhong Zhang
  • Publication number: 20240168567
    Abstract: The various implementations described herein include methods and systems for power-efficient processing of neuromuscular signals. In one aspect, a method includes: (i) obtaining a first set of neuromuscular signals; (ii) after determining, using a low-power detector, that the first set of neuromuscular signals require further processing to confirm that a predetermined in-air hand gesture has been performed: (a) processing the first set of neuromuscular signals using a high-power detector; and (b) in accordance with a determination that the processing indicates that the predetermined in-air hand gesture did occur, registering an occurrence of the predetermined in-air hand gesture; (iii) receiving a second set of neuromuscular signals; and (iv) after determining, using the low-power detector and not using the high-power detector, that a different predetermined in-air hand gesture was performed, performing an action in response to the different predetermined in-air hand gesture.
    Type: Application
    Filed: September 19, 2023
    Publication date: May 23, 2024
    Inventors: Alexandre Barachant, Bijan Treister, Shan Chu, Igor Gurovski, Chetan Parag Gupta, Tahir Turan Caliskan, Pascal Alexander Bentioulis, Viswanath Sivakumar, Zhong Zhang, Ramzi Elkhater, Maciej Lazarewicz, Per-Erik Bergstrom, Peter Andrew Matsimanis, Chengyuan Yan
  • Patent number: 11980030
    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 7, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 11974431
    Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Zhiliang Xia
  • Publication number: 20240107761
    Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 28, 2024
    Inventors: Di Wang, Zhong Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo, Wei Xie