Abstract: The various implementations described herein include methods and systems for power-efficient processing of neuromuscular signals. In one aspect, a method includes: (i) obtaining a first set of neuromuscular signals; (ii) after determining, using a low-power detector, that the first set of neuromuscular signals require further processing to confirm that a predetermined in-air hand gesture has been performed: (a) processing the first set of neuromuscular signals using a high-power detector; and (b) in accordance with a determination that the processing indicates that the predetermined in-air hand gesture did occur, registering an occurrence of the predetermined in-air hand gesture; (iii) receiving a second set of neuromuscular signals; and (iv) after determining, using the low-power detector and not using the high-power detector, that a different predetermined in-air hand gesture was performed, performing an action in response to the different predetermined in-air hand gesture.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: A three-dimensional (3D) memory device includes a memory stack including a memory block. The memory block includes a memory array structures and a staircase structure in a first lateral direction, and fingers in a second lateral direction perpendicular to the first lateral direction. The fingers include a first finger and a second finger. The 3D memory device also includes a source-select-gate (SSG) cut structure extending through a portion of the memory stack and between the first finger and the second finger. The staircase structure includes a first staircase connected to first memory cells in the first finger and a second staircase connected to second memory cells in the second finger.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A terminal control system and method, and a terminal device are provided. The terminal control system includes: a detection chip and at least one terminal key arranged on a side surface of a terminal device. The detection chip is connected to the terminal key. The terminal key is configured to generate an inductive capacitance and an interelectrode capacitance corresponding to an external control instruction, in response to a reception of the external control instruction. The detection chip is configured to detect the inductive capacitance and the interelectrode capacitance; determine inductive capacitance variation corresponding to the inductive capacitance and interelectrode capacitance variation corresponding to the interelectrode capacitance; determine a control type corresponding to the control instruction according to the inductive capacitance variation and the interelectrode capacitance variation; and trigger the terminal device to perform a control operation corresponding to the control type.

Abstract: A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: Biotin derivatives, methods of using the biotin derivatives and kits comprising the biotin derivatives.

Abstract: A 3D memory device includes a memory stack including a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of strings in a second lateral direction. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone. The 3D memory device also includes a SSG cut structure. The SSG cut structure includes a first portion between a first string and a second string and extends in the bridge structure in the first lateral direction. The staircase zone includes a first staircase conductively connected to first memory cells in the first string through the bridge structure and a second staircase conductively connected to second memory cells in the second string in the first memory array structure through the bridge structure.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure, and a slit structure extending. The stack structure includes interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure. Each one of the conductive layers has a thickened portion in the staircase structure. The thickened portion extends along a first direction. The slit structure extends through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened portions of the conductive layers.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device also includes a plurality of landing structures each over a respective conductive layer at a respective stair. Each of the landing structures includes a first layer having a first material and a second layer having a second material, the first layer being over the second layer.

Abstract: Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

Abstract: A method for detecting abnormal scene may include obtaining data relating to a video scene, identify at least two motion objects in the video scene based on the data and determining a first motion feature relating to the at least two motion objects based on the data. The method may also include determining a second motion feature relating to at least one portion of each of the at least two motion objects based on the data. The method may further include determining whether the at least two motion objects are involved in a fight based on the first motion feature and the second motion feature.

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.