Abstract: In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.

Abstract: A method and system using face tracking and object tracking is disclosed. The method and system use face tracking, location, and/or recognition to enhance object tracking, and use object tracking and/or location to enhance face tracking.

Abstract: An atmospheric pressure water ion generating device is arranged in a triphase organic matter pyrolysis system which includes a steam generating device and a pyrolysis and carbonization reaction device. The water ion generating device includes a connecting pipe connected with the steam generating device, and having an interior that is penetrated, a heating tube having a first end connected with the connecting pipe and having an interior provided with an air channel, and a spraying head connected with a second end of the heating tube, and having an interior that is tapered. The air channel has a surface provided with an alloy catalyst layer. The spraying head is provided with a nozzle which is connected with the pyrolysis and carbonization reaction device.

Abstract: A method may include obtaining real-time image data relating to at least one scene acquired by a camera and identifying a plurality of real-time first features relating to a plurality of subjects from the real-time image data. The method may include determining one or more first estimated values corresponding to the plurality of real-time first features, the first estimated values being represented by a first coordinate system. The method may further include obtaining one or more first reference values corresponding to the plurality of real-time first features, the first reference values being represented by a second coordinate system, each of the first estimated values corresponding to one of the first reference values. The method may further include determining one or more real-time target parameters of the camera based on the first estimated values and the first reference values.

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes a first and a second staircase structures, wherein the first staircase structure is formed in the first film stack and the second staircase structure is formed in the second film stack. The first and second staircase structures are next to each other with an offset.

Abstract: Three-dimensional memory devices and fabricating methods therefore are disclosed. The memory device can comprise a stack structure comprising a plurality of gate layers, a plurality of first insulating layers, and a plurality of second insulating layers. The stack structure has a staircase region comprising a plurality of stair structures. Each stair structure comprises a first portion of the stair structure comprising one gate layer and a first portion of one first insulating layer, and a second portion of the stair structure comprising a second portion of the one first insulating layer and a second insulating layer. The memory device can further comprise at least one contact structure each located on a top surface of one of the plurality of stair structures, and at least one contact portion in contact with the at least one contact structure.

Abstract: A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: The present invention provides a curable pressure-sensitive adhesive composition, including a reactive polyacrylate, a liquid epoxy resin, a solid epoxy resin, a hydroxyl-containing compound, and a photoinitiator of specific contents. The curable pressure-sensitive adhesive composition may further include an epoxy silane coupling agent of a specific content. In addition, the present invention further provides a curable pressure-sensitive adhesive tape and a battery pack including the curable pressure-sensitive adhesive composition. The curable pressure-sensitive adhesive composition and the curable pressure-sensitive adhesive tape provided by the present invention have at least good bonding strength and good anti-warping performance, and can improve the stability and safety of battery packs.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: A method for smart door operation implemented on a computer may include obtaining image data of one or more subjects. The image data may be acquired by one or more cameras in communication with the computer. The method may also include determining, based on the image data, one or more gait features of at least one of the one or more subjects and determining, at least in part based on the one or more gait features, identity information of the at least one of the one or more subjects. The method may further include sending an unlocking signal to a lock based on the unlocking signal so that the lock is unlocked.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

Abstract: A 3D memory device includes a memory stack having a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of fingers in a second lateral. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone in the second lateral direction. The 3D memory device also includes a source-select-gate (SSG) cut structure extending in a SSG of the memory stack and between adjacent ones of the plurality of fingers of the memory block. The SSG cut structure is between a first finger and a second finger, the first finger includes a string. The staircase zone includes a staircase conductively connected to memory cells in the string in each of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: A 3D memory device includes a memory stack including a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of strings in a second lateral direction. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone. The 3D memory device also includes a SSG cut structure. The SSG cut structure includes a first portion between a first string and a second string and extends in the bridge structure in the first lateral direction. The staircase zone includes a first staircase conductively connected to first memory cells in the first string through the bridge structure and a second staircase conductively connected to second memory cells in the second string in the first memory array structure through the bridge structure.

Abstract: A terminal control system and method, and a terminal device are provided. The terminal control system includes: a detection chip and at least one terminal key arranged on a side surface of a terminal device. The detection chip is connected to the terminal key. The terminal key is configured to generate an inductive capacitance and an interelectrode capacitance corresponding to an external control instruction, in response to a reception of the external control instruction. The detection chip is configured to detect the inductive capacitance and the interelectrode capacitance; determine inductive capacitance variation corresponding to the inductive capacitance and interelectrode capacitance variation corresponding to the interelectrode capacitance; determine a control type corresponding to the control instruction according to the inductive capacitance variation and the interelectrode capacitance variation, and trigger the terminal device to perform a control operation corresponding to the control type.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.

Abstract: Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.