Abstract: A terminal control system and method, and a terminal device are provided. The terminal control system includes: a detection chip and at least one terminal key arranged on a side surface of a terminal device. The detection chip is connected to the terminal key. The terminal key is configured to generate an inductive capacitance and an interelectrode capacitance corresponding to an external control instruction, in response to a reception of the external control instruction. The detection chip is configured to detect the inductive capacitance and the interelectrode capacitance; determine inductive capacitance variation corresponding to the inductive capacitance and interelectrode capacitance variation corresponding to the interelectrode capacitance; determine a control type corresponding to the control instruction according to the inductive capacitance variation and the interelectrode capacitance variation; and trigger the terminal device to perform a control operation corresponding to the control type.

Abstract: A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: Biotin derivatives, methods of using the biotin derivatives and kits comprising the biotin derivatives.

Abstract: A 3D memory device includes a memory stack including a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of strings in a second lateral direction. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone. The 3D memory device also includes a SSG cut structure. The SSG cut structure includes a first portion between a first string and a second string and extends in the bridge structure in the first lateral direction. The staircase zone includes a first staircase conductively connected to first memory cells in the first string through the bridge structure and a second staircase conductively connected to second memory cells in the second string in the first memory array structure through the bridge structure.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device also includes a plurality of landing structures each over a respective conductive layer at a respective stair. Each of the landing structures includes a first layer having a first material and a second layer having a second material, the first layer being over the second layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure, and a slit structure extending. The stack structure includes interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure. Each one of the conductive layers has a thickened portion in the staircase structure. The thickened portion extends along a first direction. The slit structure extends through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened portions of the conductive layers.

Abstract: Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

Abstract: A method for detecting abnormal scene may include obtaining data relating to a video scene, identify at least two motion objects in the video scene based on the data and determining a first motion feature relating to the at least two motion objects based on the data. The method may also include determining a second motion feature relating to at least one portion of each of the at least two motion objects based on the data. The method may further include determining whether the at least two motion objects are involved in a fight based on the first motion feature and the second motion feature.

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.

Abstract: The present invention provides a composite plate, a composite plate roughening device, and a method for manufacturing a composite plate, and relates to the technical field of metal plate materials. The composite plate includes a first plate and a second plate, wherein a first side surface of the first plate is provided with striations, the first side surface of the second plate and the first side surface of the first plate are rolled to connect, and the striations of which adjacent ones have a pitch of 0.005 mm to 0.03 mm account for more than 90% of all the striations.

Abstract: The present invention relates to the technical field of material processing and provides a method for making a metal material composite, including: contacting a first surface of a first plate with a second surface of a second plate; placing the first plate and the second plate in a recess in a circumferential direction of a first roller such that a third surface of the second plate contacts a bottom wall of the recess in a circumferential, the third surface being opposite the second surface, the first plate having a greater hardness than the second plate; and controlling a first roller and a second roller to rotate, thereby rolling to combine the first plate and the second plate into a composite plate, where a fourth surface of the first plate contacts a surface of the second roller and the fourth surface is opposite the first surface during the rolling.

Abstract: A system for motion detection may include at least one storage medium that includes a set of instructions, and at least one processor in communication with the at least one storage medium. When executing the set of instructions, the at least one processor may be configured to cause the system to obtain data related to a video scene of a space from at least one video camera; detect an object in the video scene; classify the object as a human object or a non-human object; when the object is classified as a human object, track movements of the human object; and determine a posture of the human object in the video scene based on the movements of the human object.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: Biotin derivatives, methods of using the biotin derivatives and kits comprising the biotin derivatives.