Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, the 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in an intermediate of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the memory array structure. The stairs include a stair above one or more dielectric pairs. The stair includes a conductor portion electrically connected to the bridge structure and is electrically connected to the memory array structure through the bridge structure. Along a second lateral direction perpendicular to the lateral direction and away from the bridge structure, a width of the conductor portion decreases.

Abstract: A semiconductor device has a stack formed of word line layers and insulating layers that are alternatingly arranged over a substrate. A first connection region is arranged between first array regions in the stack, and a first separation structure positioned along first sides of the first connection region and the first array regions. The first separation structure extends through the stack into the substrate. A second separation structure is positioned along opposing second sides of the first connection region and the first array regions. The second separation structure includes array separation structures positioned along the second sides of the first array regions and a connection separation structure positioned along the second side of the first connection region. The connection separating structure is arranged between and aligned with the array separation structures, and further extends through the stack into the substrate.

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: In a method for fabricating a semiconductor device, an initial stack is formed. The initial stack is formed of sacrificial layers and insulating layers that are alternatingly disposed over a substrate, and includes a first connection region, a first array region, and a second connection region that are disposed sequentially. A first initial staircase is formed in the first connection region and formed in a first group of sacrificial layers and insulating layers. A first top select gate staircase is formed in the second connection region, and formed in a second group of sacrificial layers and insulating layers. An etching process is subsequently performed in the first connection region to shift the first initial staircase toward the substrate along a vertical direction perpendicular to the substrate so as to form a first bottom select gate staircase.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device and form a stack upon the substrate. The semiconductor device includes an array of channel structures that are formed in an array region of the stack. Further, the semiconductor device includes a first staircase formed of a first section of the stack in a connection region upon the substrate, and a second staircase formed of a second section of the stack in the connection region upon the substrate. In addition, the semiconductor device includes a dummy staircase formed of the first section of the stack and disposed between the first staircase and the second staircase in the connection region.

Abstract: The present invention discloses a packet transmission method and user equipment. The method includes: transmitting, by a sending node, multiple packets to a receiving node; receiving multiple acknowledgement packets from the receiving node; after determining, based on the received multiple acknowledgement packets, that a first packet is lost, retransmitting the first packet; and if it is detected that the retransmitted packet is lost, continuously retransmitting, by the sending node, the first packet to the receiving node in a preset time interval for at least twice. According to the solutions of the present invention, the retransmitted packet can be detected and recovered in time after the retransmitted packet is lost, thereby reducing a quantity of times of timeout retransmission, improving a transmission rate, moreover, reducing a packet loss probability of a retransmitted packet, and further reducing a probability of timeout retransmission.

Abstract: A triphase organic matter pyrolysis system includes multiple devices cooperating with each other. The feeding device delivers organic matters into the preheating device. The preheated organic matters are delivered into the pyrolysis and carbonization reaction device. The steam generating device produces a saturated steam which is delivered into the water ion generating device which heats the saturated steam into a superheated steam which is dissociated into water ions which are delivered into the pyrolysis and carbonization reaction device. The water ions cut, dissociates and carbonizes the organic matters to form carbon residues and gas-liquid wastes. The heat energy is recycled by the heat recycle device and is delivered into the preheating device. The gas-liquid wastes are processed by the gas-liquid separation device and the gas purifying device to form gas and liquid that are harmless.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes gate layers and insulating layers that are stacked alternatingly along a direction perpendicular to a substrate of the semiconductor device in an array region upon the substrate. Further, the semiconductor device includes an array of channel structures that is formed in the array region. The gate layers and the insulating layers are stacked in a staircase form with stair steps having non-uniform stair depths in a connection region upon the substrate. Further, the semiconductor device includes contact structures to the gate layers. The contact structures are formed on the stair steps that have the non-uniform stair depths.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into first and second memory array structures. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. Each staircase includes divisions in a second lateral direction perpendicular to the first lateral direction at different depths. At least one stair in the first pair of staircases is electrically connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The bridge structure includes a lower wall portion and an upper staircase portion. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: The disclosed systems may include systems and methods for clock synchronization under random transmission delay conditions. Additionally, systems and methods for horizon leveling for wrist captured images may be disclosed. In addition, the disclosed may include methods, systems, and devices for batch message transfer. The disclosed methods may also include a mobile computing device receiving an indication to initiate an emergency voice call by a user of the mobile computing device and initiating an Internet Protocol Multimedia Subsystem (IMS) emergency call. In addition, systems, methods, and devices for automatic content display may be disclosed. Various other related methods and systems are also disclosed.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.