Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.

Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

Abstract: The system for lighting control may include a non-transitory storage medium storing executable instructions for lighting control, a communication component operatively connected to the non-transitory storage medium, at least one imaging device configured to capture images related to an area, and one or more illuminating device configured to light the area. The system may also include at least one processor in communication with the non-transitory storage medium. When executing the set of instructions, the at least one processor may cause the system to obtain image data relating to an area captured by the at least imaging device and determine at least one parameter relating to at least one of the one or more illuminating devices. The system may further include a control component configured to operate the at least one of the one or more illuminating devices to light the area based on the determined at least one parameter.

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.

Abstract: A method and system using face tracking and object tracking is disclosed. The method and system use face tracking, location, and/or recognition to enhance object tracking, and use object tracking and/or location to enhance face tracking.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: In an example of the present disclosure, 3D memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.

Abstract: Embodiments of staircase structures of a three-dimensional memory device and fabrication method thereof are disclosed. The semiconductor structure includes a first and a second film stacks, wherein the first film stack is disposed over the second film stack and has M1 number of layers. The second film stack has M2 number of layers. M1 and M2 are whole numbers. The semiconductor structure also includes an upper staircase structure and a lower staircase structure, wherein the upper staircase structure is formed in the first film stack and the lower staircase structure is formed in the second film stack. The upper and lower staircase structures are next to each other with an offset.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, the 3D memory device includes a memory array structure and a staircase structure. The staircase structure is located in an intermediate of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the memory array structure. The stairs include a stair above one or more dielectric pairs. The stair includes a conductor portion electrically connected to the bridge structure and is electrically connected to the memory array structure through the bridge structure. Along a second lateral direction perpendicular to the lateral direction and away from the bridge structure, a width of the conductor portion decreases.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.