Patents by Inventor Zigmund Ramirez Camacho

Zigmund Ramirez Camacho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120018865
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having an upper structure, upper protrusions, and a base side facing away from the upper structure and the upper protrusions; forming tie bars in the leadframe with an opening surrounding the upper structure, the tie bars connected to the upper structure and exposed on the base side; connecting an integrated circuit to the upper protrusions; applying an encapsulant over the integrated circuit, over the upper structure, and in the opening with the base side exposed; removing the tie bars exposing a first surface and a second surface of the encapsulant below the first surface, and forming a die paddle from the upper structure and exposed from the second surface; and removing the leadframe from the base side forming island terminals from the upper protrusions exposed from the second surface and isolated from the die paddle.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 26, 2012
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8080867
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: December 20, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Publication number: 20110298108
    Abstract: A non-leaded integrated circuit package system includes: a die paddle of a lead frame; a dual row of terminals including an outer terminal and an inner terminal; and an inner terminal and an adjacent inner terminal to form a fused lead.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Inventors: Jeffrey D. Punzalan, Byung Tai Do, Henry D. Bathan, Zigmund Ramirez Camacho
  • Publication number: 20110298113
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8072047
    Abstract: An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: December 6, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Publication number: 20110291251
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first lead adjacent and staggered to a second lead, the first lead having a first external connection portion with a first external conductive layer and a first internal connection portion, the first external connection portion oriented laterally outwards from the first internal connection portion, and the second lead having a second external connection portion with a second external conductive layer and a second internal connection portion; connecting an integrated circuit device with the first internal connection portion and with the second internal connection portion; forming an encapsulation over the integrated circuit device with the first lead and the second lead exposed; and forming a solder mask on the encapsulation, on the first lead, and on the second lead with the first external conductive layer and the second external conductive layer exposed from the solder mask.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8067825
    Abstract: An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Abelardo Jr. Hadap Advincula, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • Publication number: 20110284842
    Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20110284999
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Publication number: 20110285001
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Application
    Filed: August 1, 2011
    Publication date: November 24, 2011
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 8062934
    Abstract: An integrated circuit package system comprising: forming leads adjacent a die paddle having a die pad extension; forming a region having one of the leads depopulated for the die pad extension; and connecting an integrated circuit die to the die pad extension.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8043894
    Abstract: An integrated circuit package system includes forming a first external interconnect having both a first side and a second side that is an opposing side to the first side; forming a first encapsulation around a first integrated circuit and the first external interconnect with the first side, the second side, and the first active side of the first integrated circuit exposed; forming a planar interconnect between the first active side and the second side; forming a second encapsulation covering the planar interconnect and the first active side; connecting a second integrated circuit over the first integrated circuit and the first side; and forming a top encapsulation over the second integrated circuit.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: October 25, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Henry Descalzo Bathan
  • Patent number: 8039947
    Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 8035207
    Abstract: A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: October 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Jose Alvin Caparas, Lionel Chien Hui Tay
  • Publication number: 20110233752
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar with the lead; connecting an integrated circuit and the lead; attaching a jumper interconnect between the elevated contact and the lead; and forming an encapsulant over the integrated circuit, the lead, the die pad, the elevated contact, and the jumper interconnect, the encapsulant having a recess in a base side with the elevated contact exposed in the recess and the lead exposed from the base side.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20110233753
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the inner post and the outer post; mounting an integrated circuit over a paddle first side, the paddle first side co-planar with the outer post; connecting a first jumper interconnect between the integrated circuit and the jumper pad; connecting a second jumper interconnect between the jumper pad and the outer post; and forming an encapsulation over paddle, the integrated circuit, the first jumper interconnect, the jumper pad, and the second jumper interconnect.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Publication number: 20110227211
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base panel having a first side with a cavity and a second side opposite the first side; connecting an integrated circuit device and the first side; applying a resist mask having an opening on the second side, the opening offset from the cavity; forming a bump contact in the opening; applying an encapsulation in the cavity over the integrated circuit device and the first side; and forming a package lead by removing a portion of the base panel under the cavity, a flared tip of the package lead intersecting a base side of the encapsulation.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 22, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8022514
    Abstract: An integrated circuit package system including forming a leadframe having a lead with a leadfinger support of a predetermined height, and attaching an integrated circuit die with an electrical interconnect at a predetermined collapse height determined by the predetermined height of the leadfinger support.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 20, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Jeffrey D. Punzalan
  • Patent number: 8022539
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead frame having contact pads and connection leads; coupling a base integrated circuit to the contact pads; coupling a chip interconnect between the base integrated circuit, the connection leads, the contact pads, or a combination thereof; molding a package body on the connection leads, the base integrated circuit, and the chip interconnects, including having the contact pads exposed; and forming a bottom surface on the package body including forming the connection leads to be coplanar with the bottom surface.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: September 20, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8003443
    Abstract: A non-leaded integrated circuit package system is provided providing a die paddle of a lead frame, forming a dual row of terminals including an outer terminal and an inner terminal, and selectively fusing an inner terminal and an adjacent inner terminal to form a fused lead.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: August 23, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Byung Tai Do, Henry D. Bathan, Zigmund Ramirez Camacho