Patents by Inventor Zigmund Ramirez Camacho

Zigmund Ramirez Camacho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit packaging system with isolated pads and method of manufacture thereof
    Patent number: 7998790
    Abstract: A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: August 16, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Integrated circuit package system with laminate base
    Patent number: 7993939
    Abstract: An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: August 9, 2011
    Assignee: STATS Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Leadless integrated circuit packaging system and method of manufacture thereof
    Patent number: 7994629
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Zigmund Ramirez Camacho
  • ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
    Publication number: 20110180928
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110169151
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.
    Type: Application
    Filed: December 6, 2010
    Publication date: July 14, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Multiple flip-chip integrated circuit package system
    Patent number: 7977579
    Abstract: An integrated circuit package system includes forming a multi-tier substrate, and attaching a plurality of integrated circuits on the multi-tier substrate.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Zigmund Ramirez Camacho, Jr., Arnel Trasporto, Jeffrey D. Punzalan
  • Integrated circuit package system with interference-fit feature
    Patent number: 7977778
    Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Multi-layer package-on-package system
    Patent number: 7977780
    Abstract: A package-on-package system includes: providing a bottom package module incorporating a bottom package substrate; attaching a central internal stacking module, incorporating a central interposer, on top of the bottom package module; placing a spacer on the top surface of the central internal stacking module; mounting a first top package module, incorporating a first top interposer with an opening, on the spacer; and enclosing at least portions of the bottom package module, the central internal stacking module, and the first top package module with an encapsulant.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Mountable integrated circuit package-in-package system
    Patent number: 7977779
    Abstract: A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Integrated circuit package system with dual connectivity
    Patent number: 7977782
    Abstract: An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integrated circuit die. The forming the package encapsulation includes partially exposing the top contact portion at the top side, and partially exposing the bottom contact portion along the bottom side with the bottom contact portion extending beyond a nonhorizontal portion of the package encapsulation.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Jose Alvin Caparas, Lionel Chien Hui Tay
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110140261
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Philip Lyndon Cablao, Lionel Chien Hui Tay, Frederick Rodriguez Dahilig
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REMOVABLE BACKING ELEMENT HAVING PLATED TERMINAL LEADS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110140251
    Abstract: A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110140252
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Erwin Aguas Sangalang, Lionel Chien Hui Tay
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110140287
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a device over a substrate including a bond wire pad row located between a perimeter of the substrate and the device; configuring the bond wire pad row to include three sided bond wire pads that horizontally overlap; and forming an interconnection between the device and the bond wire pad row.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 16, 2011
    Inventors: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
    Publication number: 20110129965
    Abstract: A method for manufacturing a semiconductor package system includes: providing a leadframe, having an open center, with leads adjacent to a peripheral edge of the leadframe; making a die support pad, formed without tie bars, separately from the leadframe; providing a coverlay tape for positioning the support pad centered within the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the leads; and connecting a bonding pad on the semiconductor die to one of the leads using a bonding wire.
    Type: Application
    Filed: February 8, 2011
    Publication date: June 2, 2011
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Lionel Chien Hui Tay
  • PACKAGE SYSTEM WITH A SHIELDED INVERTED INTERNAL STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110127653
    Abstract: A method of manufacture of a package system includes: providing a base package substrate having conductive elements; providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate; covering at least portions of the first encapsulant in the internal stacking module with an electromagnetic interference shield, the electromagnetic interference shield shaped to have an outside face; mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Inventors: Reza Argenty Pagaila, Zigmund Ramirez Camacho, Henry Descalzo Bathan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110127661
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Jairus Legaspi Pisigan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110115065
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a planar support structure having a cavity; forming a terminal within the cavity with the terminal coplanar with the planar support structure; forming a conductive pathway on the terminal and the planar support structure with the conductive pathway having a route portion and an interconnect attach portion at the end of the route portion; connecting a device and the interconnect attach portion with the interconnect attach portion towards the device; and forming an encapsulation over the planar support structure covering the conductive pathway and the device.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 19, 2011
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Allan P. Ilagan, Philip Lyndon Cablao
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110108966
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a conductive layer having a first surface and a second surface; forming first concave trenches in the first surface of the conductive layer and the first concave trenches are connected by a first flat region of the first surface; connecting an integrated circuit to the first flat region with a conductive interconnect; encapsulating the integrated circuit with an encapsulation that fills the first concave trenches; and forming second concave trenches having a similar size in the second surface of the conductive layer with the second concave trenches connected by a second flat region that is larger than the first flat region, and the second concave trenches are formed through the conductive layer to expose the encapsulation.
    Type: Application
    Filed: March 23, 2010
    Publication date: May 12, 2011
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110101542
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 5, 2011
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan