Patents by Inventor Zoran Krivokapic

Zoran Krivokapic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple-gate MOS device and method for making the same
    Patent number: 6919250
    Abstract: A method for forming a semiconductor device with more than two gates involves the forming of a stack of n-conductive gate electrodes, where n>2. Silicon is formed around the gate stack and the silicon is doped to form source/drain regions. The multiple gates maximize the drive current for a given silicon area.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 19, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Semiconductor device having conductive structures formed near a gate electrode
    Patent number: 6917068
    Abstract: A semiconductor device is provided by forming a gate electrode and a dielectric layer below and adjacent the side surfaces of the gate electrode. Relatively thin conductive structures are formed within the dielectric layer. The conductive structures may be used as a floating gate electrode for a memory device. The conductive structures may also be used to control a threshold voltage for a logic device.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: July 12, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Method of manufacturing a semiconductor device having a MESA structure
    Patent number: 6913959
    Abstract: A strained semiconductor device suitable for use in an integrated circuit and a method for manufacturing the strained semiconductor device. A mesa isolation structure is formed from a semiconductor-on-insulator substrate. A gate structure is formed on the mesa isolation structure. The gate structure includes a gate disposed on a gate dielectric material and has two sets of opposing sidewalls. Semiconductor material is selectively grown on portions of the mesa isolation structure adjacent a first set of opposing sidewalls of the gate structure and then doped. The doped semiconductor material is silicided and protected by a dielectric material. The gate is silicided wherein the silicide wraps around a second set of opposing sidewalls and stresses a channel region of the semiconductor device.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: July 5, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Strained channel FinFET
    Patent number: 6897527
    Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: May 24, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
  • Self aligned damascene gate
    Publication number: 20050104091
    Abstract: A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 19, 2005
    Inventors: Cyrus Tabery, Shibly Ahmed, Matthew Buynoski, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang, Chih-Yuh Yang, Bin Yu
  • Straddled gate FDSOI device
    Patent number: 6888198
    Abstract: A straddled gate device, and a method of producing such device, formed on a semiconductor-on-insulator (SOI) substrate having active regions defined by isolation regions and an insulator layer. The device includes a first gate defining a first channel region interposed between a source and a drain formed within the active region of the SOI substrate. Additionally, the device includes a second gate straddling the first gate defining second channel regions interposed between the first channel region and the source and the drain. Further still, the device includes a contact connecting the first gate with the second gate wherein when the device is in the off state (Ioff) the first channel region and second channel regions define a long channel and when the device is in the on state (Ion) the first channel region defines a short channel.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: May 3, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Shallow trench isolation (STI) region with high-K liner and method of formation
    Publication number: 20050073022
    Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
    Type: Application
    Filed: August 18, 2003
    Publication date: April 7, 2005
    Inventors: Olov Karlsson, HaiHong Wang, Bin Yu, Zoran Krivokapic, Qi Xiang
  • Metal gate electrode using silicidation and method of formation thereof
    Patent number: 6873030
    Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: March 29, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Witold Maszara, Zoran Krivokapic
  • Finfet gate formation using reverse trim of dummy gate
    Patent number: 6864164
    Abstract: A method of forming a gate electrode for a fin field effect transistor (FinFET) includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a carbon layer over the oxide layer and forming a trench in the oxide layer and the carbon layer, where the trench crosses over the fin. The method also includes filling the trench with a material to form the gate electrode.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 8, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Cyrus E. Tabery
  • Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
    Patent number: 6861307
    Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Zheng, Mark W. Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey
  • Method for forming tri-gate FinFET with mesa isolation
    Patent number: 6855583
    Abstract: A method forming a tri-gate fin field effect transistor includes forming an oxide layer over a silicon-on-insulator wafer comprising a silicon layer, and etching the silicon and oxide layers using a rectangular mask to form a mesa. The method further includes etching a portion of the mesa using a second mask to form a fin, forming a gate dielectric layer over the fin, and forming a tri-gate over the fin and the gate dielectric layer.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: February 15, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Bin Yu
  • Method of manufacturing a semiconductor device having a U-shaped gate structure
    Publication number: 20050006666
    Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 13, 2005
    Inventors: Bin Yu, Shibly Ahmed, Judy An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
  • Two transistor NOR device
    Patent number: 6842048
    Abstract: A NOR gate includes is constructed with two asymmetric FinFET type transistors instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 11, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Ming-Ren Lin, Haihong Wang
  • Semiconductor device and method of manufacture
    Publication number: 20050003593
    Abstract: A strained semiconductor device suitable for use in an integrated circuit and a method for manufacturing the strained semiconductor device. A mesa isolation structure is formed from a semiconductor-on-insulator substrate. A gate structure is formed on the mesa isolation structure. The gate structure includes a gate disposed on a gate dielectric material and has two sets of opposing sidewalls. Semiconductor material is selectively grown on portions of the mesa isolation structure adjacent a first set of opposing sidewalls of the gate structure and then doped. The doped semiconductor material is silicided and protected by a dielectric material. The gate is silicided wherein the silicide wraps around a second set of opposing sidewalls and stresses a channel region of the semiconductor device.
    Type: Application
    Filed: June 23, 2003
    Publication date: January 6, 2005
    Inventor: Zoran Krivokapic
  • Semiconductor device having a U-shaped gate structure
    Patent number: 6833588
    Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 21, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
  • Interferometric lithography using reflected light from applied layers
    Patent number: 6830850
    Abstract: An interferometric lithography method includes providing a first layer of material over a substrate and providing a second layer of material over the first layer of material. The method further includes providing a layer of photoresist over the first and second layers of material and providing coherent light to the first and second layers. The coherent light has an intensity insufficient to chemically transform the photoresist. The coherent light reflects off the first and layers to interfere with an intensity sufficient to chemically transform the photoresist.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Bhanwar Singh
  • Monos device having buried metal silicide bit line
    Patent number: 6828199
    Abstract: A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: December 7, 2004
    Assignees: Advanced Micro Devices, Ltd., Fujitsu Limited
    Inventors: Jusuke Ogura, Mark T. Ramsbey, Arvind Halliyal, Zoran Krivokapic, Minh Van Ngo, Nicholas H. Tripisas
  • Multiple-gate MOS device and method for making the same
    Publication number: 20040235283
    Abstract: A method for forming a semiconductor device with more than two gates involves the forming of a stack of n-conductive gate electrodes, where n>2. Silicon is formed around the gate stack and the silicon is doped to form source/drain regions. The multiple gates maximize the drive current for a given silicon area.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Zoran Krivokapic
  • Ultra-thin fully depleted SOI device and method of fabrication
    Patent number: 6815297
    Abstract: A fully depleted SOI FET and methods of formation are disclosed. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source, a drain and a body disposed between the source and the drain are formed from the layer of semiconductor material. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess. The gate defines a channel in the body and includes a gate electrode spaced apart from the body by a high-K gate dielectric.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: November 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Witold P. Maszara
  • Strained channel finfet
    Patent number: 6803631
    Abstract: A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: October 12, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu