Patents by Inventor Zoran Krivokapic

Zoran Krivokapic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Strained channel FinFET
    Publication number: 20040195627
    Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.
    Type: Application
    Filed: April 28, 2004
    Publication date: October 7, 2004
    Inventors: Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
  • Narrow fin finfet
    Publication number: 20040197975
    Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 7, 2004
    Inventors: Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Haihong Wang, Bin Yu
  • STRAINED CHANNEL FINFET
    Publication number: 20040145019
    Abstract: A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.
    Type: Application
    Filed: January 23, 2003
    Publication date: July 29, 2004
    Inventors: Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
  • FinFET-based SRAM cell
    Patent number: 6765303
    Abstract: A SRAM cell includes a single FinFET and two resonant tunnel diodes. The FinFet has multiple channel regions formed from separate fins. The resonant tunnel diodes may be formed from FinFET type fins. In particular, the resonant diodes may includes a thin, undoped silicon region surrounded by a dielectric. The SRAM cell is small and provides fast read/write access times.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Matthew S. Buynoski
  • Narrow fin FinFET
    Patent number: 6762483
    Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: July 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Haihong Wang, Bin Yu
  • Two transistor nor device
    Publication number: 20040100306
    Abstract: A NOR gate includes is constructed with two asymmetric FinFET type transistors instead of the conventional four-transistor NOR gate. The reduction in the number of transistors from four down to two allows for significant improvements in integrated semiconductor circuits.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Inventors: Zoran Krivokapic, Judy Xilin An, Ming-Ren Lin, Haihong Wang
  • Self-aligned triple gate silicon-on-insulator (SOI) device
    Patent number: 6727546
    Abstract: A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region. Also disclosed is a method for manufacturing a transistor device.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: April 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Matthew Buynoski
  • Method of making a hybrid SOI device that suppresses floating body effects
    Patent number: 6727149
    Abstract: A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p+ regions adjacent each of the SOI transistor source/drain regions to adjust the SOI transistor threshold voltage. To suppress punch-through current, an additional implant step is carried out to form second p+ regions adjacent first implant regions.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: April 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinath Krishnan, Witold P. Maszara, Zoran Krivokapic
  • Semiconductor device having a U-shaped gate structure
    Publication number: 20040075121
    Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Inventors: Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
  • Double and triple gate MOSFET devices and methods for making same
    Publication number: 20040075122
    Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
  • Method of making a self-aligned triple gate silicon-on-insulator device
    Patent number: 6716684
    Abstract: A self-aligned transistor and method making a self-aligned transistor, the transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zoran Krivokapic, Matthew Buynoski
  • Method and system for forming a long channel device
    Patent number: 6716706
    Abstract: The present invention is a method of forming a channel device. The method comprises the steps of providing at least one active region on a substrate wherein the active region comprises a plurality of discontinuous gate structures. The method further comprises providing an ion implantation in the substrate. In accordance with the present invention, a higher Early Voltage is achieved thereby enabling halo/pocket and LDD implants to be effectively utilized in the design of analog circuitry.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure
    Patent number: 6717212
    Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, William George En, Srinath Krishnan, Concetta E. Riccobene, Zoran Krivokapic, Judy Xilin An, Bin Yu
  • Dual damascene process using self-assembled monolayer and spacers
    Patent number: 6703304
    Abstract: A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the layer of material; etching the first self-assembled monolayer to form an aperture in the layer of material; etching the first insulative layer through the first aperture, wherein a top surface of the second insulative layer is exposed; depositing a spacer layer over the layer of material, wherein a portion of the spacer layer masks a portion of the top surface of the second insulative layer; and etching the second insulative layer.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: March 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic
  • Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
    Publication number: 20040021172
    Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Wei Zheng, Mark W. Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey
  • High-K dielectric having barrier layer for P-doped devices and method of fabrication
    Patent number: 6660578
    Abstract: A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: December 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Olov Karlsson, Qi Xiang, HaiHong Wang, Bin Yu, Zoran Krivokapic
  • Shallow trench isolation (STI) region with high-K liner and method of formation
    Patent number: 6657276
    Abstract: A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: December 2, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Olov B. Karlsson, HaiHong Wang, Bin Yu, Zoran Krivokapic, Qi Xiang
  • Metal gate electrode using silicidation and method of formation thereof
    Publication number: 20030203609
    Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.
    Type: Application
    Filed: May 7, 2003
    Publication date: October 30, 2003
    Inventors: Witold Maszara, Zoran Krivokapic
  • Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
    Patent number: 6639271
    Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 28, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Wei Zheng, Mark W. Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey
  • Copper interconnect stamping
    Patent number: 6623803
    Abstract: A method of patterning a layer of copper on a material surface includes providing a stamp having a base and a stamping surface and providing a copper plating catalyst on the stamping surface. The method can also include applying the stamping surface to the material surface, wherein a pattern of copper plating catalyst is applied to the material surface. The method can further include providing a copper solution over the copper plating catalyst, whereby a layer of copper is patterned on the material surface.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zoran Krivokapic