Abstract: An improved Silicon-On-Insulator (SOI) device structure with a thin SOI silicon layer maintains excellent Ioff DC characteristics without degrading device AC speed and characteristics. The device structure comprises double gate sidewall spacers including an inner polysilicon spacer and an outer dielectric (nitride or oxide) sidewall spacer.

Abstract: A germanium-on-insulator (GOI) device formed on a GOI structure with a buried oxide (BOX) layer disposed therein and an active layer disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The GOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: The present invention provides a semiconductor device with a channel length of approximately 0.05 microns. A semiconductor device according to the present invention, and a method for producing such a semiconductor device, comprises a control gate, a first floating gate located in proximity to the control gate, and a second floating gate located in proximity to the control gate. The present invention allows the threshold voltage of the device to be adjusted to various levels. Additionally, the device according to the present invention can be used as a very effective nonvolatile memory device.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a filled backside contact opening disposed under and in thermal contact with at least one of the anode or the cathode, the backside contact opening traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: A fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET) and methods of formation. The FET includes a T-shaped gate formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The gate includes a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.

Abstract: A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.

Abstract: A method of forming a memory device from a single transistor and a single RTD structure is provided. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon layer has a first region and a second region. The second region is masked and a transistor device is formed in the first region of the top silicon layer. Next, the first region is masked and a vertical RTD device is formed in the second region. The step of forming a vertical RTD device in the second region comprises implanting a n+ dopant to form concurrently a source and drain region of the transistor device and a generally horizontal N+ quantum well region of the vertical RTD device. The drain region of the transistor device is coupled to the quantum well region of the vertical RTD. The N+ quantum well region is disposed horizontally below a top surface of the second region.

Abstract: A method of forming a T-shaped gate for a transistor, comprising: defining a base length of the gate by forming a gate stack on a substrate; defining a contact length by forming a layer of nitride on the gate stack; and defining gate height by selectively removing portions of the nitride layer. The method may include the further step of defining a contact height by depositing a conductive layer on said gate stack.

Abstract: In the fabrication of a semiconductor structure, a silicon substrate is provided, and an insulating layer is provided on the substrate. First and second structures are provided on the insulating layer, the first structure comprising a dielectric on the insulating layer, and the second structure comprising polysilicon on the insulating layer and a dielectric on the polysilicon. Source and drain regions are formed in the silicon using the first and second structures as masks. The dielectric of the first structure is removed, the dielectric of the second structure is removed to expose the polysilicon, and a portion of the insulating layer is removed to expose portions of the silicon of the substrate. Silicide is then grown on exposed portions of silicon and the polysilicon.

Abstract: A self-aligned double gate transistor, comprising: a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region, and having a first side and a second side, the first side and the second side having a first gate oxide and a second gate oxide, respectively, formed thereon; a first silicon gate abutting said first side of said channel region on said insulator; and a second silicon gate abutting said second side of said channel on said insulator.

Abstract: A tunneling junction transistor (TJT) SRAM cell device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The SOI TJT SRAM cell device includes a first gate and a second gate stacked over one of the active regions. The first gate defines a channel interposed between a source and a drain formed within one of the active regions. The second gate includes a plurality of thin nitride layer interposed between an undoped region and the first gate electrode, a side gate electrode, and a polysilicon layer. The plurality of thin nitride layers form tunneling junctions between the electrodes. The SOI TJT SRAM cell device is electrically coupled respectively to a first and a second node; and a contact plug adjacent and in electrical contact with at least one of the source and the drain.

Abstract: A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

Abstract: A method of forming dual gate structures on first and second portions, substrate includes: providing an insulative layer over the substrate; providing a first layer of material having a first work function with the first portion of the substrate; providing a second layer of material having a second work function different than the first work function over the second portion of the substrate; patterning a third layer of material over the first and second layers of material, whereby features of the third layer of material are provided over both the first and second portions of the substrate; providing a self-assembled molecular layer over at least a portion of the features, wherein the self-assembled molecular layer has regions of etch selectivity; and etching the self-assembled molecular layer at the regions of etch selectivity until gate structures are formed over the first and second portions of the substrate.

Abstract: A method of manufacturing devices with source, drain and extension regions is provided. To achieve in the extensions a depth and dopant levels different from the source and drain regions, a channel-shaped oxide structure is formed surrounding a polysilicon gate. The channel-shaped oxide structures forms an implantation barrier over the extensions region. Thus, when the source and drain implantation is carried out at a given energy, the extension regions receives a 35-40 percent dopant dose, as compared to the dose received by the source region and the drain region.

Abstract: The present invention provides a semiconductor device with a channel length of approximately 0.05 microns. A semiconductor device according to the present invention, and a method for producing such a semiconductor device, comprises a control gate, a first floating gate located in proximity to the control gate, and a second floating gate located in proximity to the control gate. The present invention allows the threshold voltage of the device to be adjusted to various levels. Additionally, the device according to the present invention can be used as a very effective nonvolatile memory device.

Abstract: The uniformity, density and directionality of an ionized metal plasma is significantly improved by positioning a cylindrical target between an RF coil and the chamber wall and wafers above and below the coil at opposite ends of the sputtering chamber. Ions generated by electron impact are attracted to the biased substrates, thereby providing essentially void free interconnections through insulating layers having through holes with very high aspect ratios.

Abstract: A silicon on insulator (SOI) semiconductor device is provided having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The device combines the inverted region with channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.

Abstract: An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack.

Abstract: The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes.