Abstract: A fully depleted field effect transistor formed in a silicon on insulator (SOI) substrate includes a body region formed in a silicon device layer over an isolation layer of the SOI substrate. A gate is positioned above the body region and includes a base gate region adjacent the body region and a wide top gate region formed of tungsten damascene and spaced apart from the body region. An inverted T-shaped central channel region is formed between adjacent source regions and drain region in the body region.

Abstract: The disclosure relates to a system for and a method of forming a local interconnect in an integrated circuit using microcontact printing. An exemplary method of the disclosure can include applying an active agent to a stamp, stamping the stamp on a portion of an integrated circuit wafer to form an aperture in a layer of material on the integrated circuit wafer, and providing a conductive material in the aperture formed by the stamp. The stamp preferably has a wedge-shaped extrusion with a length corresponding to a length of an interconnect to be formed in the portion of the integrated circuit wafer. The conductive material in the aperture defines the interconnect. In one example, the interconnect can be as narrow as 20 to 50 nanometers (nm).

Abstract: A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

Abstract: A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.

Abstract: A semiconductor device includes a T-shaped gate electrode. The T-shaped electrode may have a metal upper layer and a semiconductor lower layer with a diffusion barrier therebetween. The metal upper layer may be used as a gate mask to control implantation of ions in a semiconductor substrate. Gate metal-semiconductor portions may be electrically coupled to both the metal upper portion and the semiconductor lower portion thereby to reduce electrical resistance in the T-shaped electrode. A method of forming source and drain regions in the semiconductor device includes using the T-shaped gate electrode as an implant mask.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors and cause shifts in the lateral placement and implant depth of TCI dopants. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. In one embodiment, a first linear or quasi-linear interpolation function is used having form: Energya=E0*(1+&bgr;*eSw/SwT), where multiplying factor &bgr; may either be a constant or a function of normalized sidewall error value, eSw/SwT. In the same embodiment, a second linear or quasi-linear interpolation function is used having form: Dosea=Dose0*(1+&agr;(L2T−L2M)/L2T), where multiplying factor &agr; is a constant or a function of normalized gate length error value, (L2T−L2M)/L2T.

Abstract: A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

Abstract: A silicon on insulator (SOI) semiconductor device is provided having a semiconductor substrate with an inverted region, an insulator, and a silicon island. The device combines the inverted region with channel doping to fully deplete the silicon island of majority carriers when the device is in the off state and both of its junctions are at ground.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.

Abstract: A tunneling junction transistor (TJT) device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The TJT device includes a gate defining a channel interposed between a source and a drain formed within one of the active regions of the SOI substrate. At least one thin nitride layer is interposed between a portion of the channel and at least one of the source and the drain.

Abstract: A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

Abstract: In a method of forming a metal gate of a semiconductor device, a substrate is provided, which includes a substrate body covered by a dielectric layer. A metal body having top and side surface is provided on the dielectric layer. A self-assembled monolayer is provided over the top and side surfaces of the metal body, and has an ordered region covering the top surface of the metal body and disordered regions covering the side surfaces of the metal body. The resulting structure is etched, the disordered regions of the self-assembled monolayer allowing etching of the side surfaces of the metal body while the ordered region of the self-assembled monolayer substantially blocks etching of the top surface of the metal body.

Abstract: A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.

Abstract: A method of forming a vertical transistor in an integrated circuit using copolymer lithography includes providing a dielectric layer over a semi-conductor substrate and depositing a layer of copolymer over the dielectric layer. The copolymer has a first polymer type and a second polymer type. The method further includes removing a portion of the first polymer type from the copolymer layer to form a void in the copolymer layer and removing a portion of the dielectric layer underlying the void to form an aperture in the dielectric layer. The method further includes providing a semiconductor material in the aperture.

Abstract: A method of fabricating a trench on an integrated circuit having first and second insulative layers includes providing a layer of material over the insulative layers, forming a first self-assembled monolayer on the metal layers, etching the first self-assembled monolayer to form a first aperature in the layer of material, etching the first and second insulative layers through the first aperature to form a first portion of the trench, forming a second self-assembled monolayer on the layer of material, etching the second self-assembled monolayer to form a second aperature in the layer of material wider than the first aperature, and etching the second insulative layer through the second aperature to form a second portion of the trench.

Abstract: A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is also disclosed.

Abstract: An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve hot-carrier lifetime while maintaining high drive currents. This is accomplished by providing polysilicon spacers for the n-channel devices and silicon nitride spacers for the p-channel devices.

Abstract: A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The method includes spacing the gate electrode from the body by a gate dielectric made from a high-K material.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.