Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.
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This application claims the benefit of the following provisionally filed U.S. Patent application: Application Ser. No. 62/260,841, filed Nov. 30, 2015, and entitled “Anti-Fuse Cell Structure;” which application is hereby incorporated herein by reference.
BACKGROUNDAnti-fuse memories include memory cells, whose terminals are disconnected before programming, and are shorted/connected after the programming. The anti-fuse memories may be based on Metal-Oxide Semiconductor (MOS) technology, wherein the gate dielectrics of MOS capacitors/transistors may be broken down to cause the gate and the source/drain regions of a programming capacitor/transistor to be interconnected. Anti-fuse cells have the advantageous features of reverse-engineering proofing, since the programming states of the anti-fuse cells cannot be determined through reverse engineering.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
An anti-fuse and the method of operating the same are provided in accordance with various exemplary embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Referring further to
Contact plugs 18 are formed at a level underlying the via-0 level, and are used to connect the vias in via-0 level to the underlying features such as the gates or the source/drain regions of the MOS capacitors and the reading devices.
In accordance with some embodiments, ends 14′ (sidewalls) of active regions 14 are overlapped by gate electrode 26A. Active regions 14 thus do not extend across gate electrode 26A. Alternatively stated, ends 14′ of active regions 14 terminate between the opposite edges 26′ and 26″ of gate electrode 26A. Hence, MOS_Cap 26 is a two-terminal device, and has a single source/drain region.
Gate electrodes 24A and 26A are electrically connected to the same word-line WL through connection module 28. Word-line WL may be in the M2 level (
A plurality of cross-sectional views are taken from
Gate electrodes 24A and 26A may be formed of metal, metal alloy, metal silicide, metal nitride, or the like. Gate dielectrics 24D and 26D may be formed of a high-k dielectric having a k value higher than 3.8. The k value may be higher than about 7.0. The high-k dielectric material may include aluminum oxide, hafnium oxide, lanthanum oxide, or the like. Gate dielectric 26D of the MOS_Cap has thickness T1. Gate dielectric 24D of the MOS_Cap has thickness T2, which is greater than thickness T1. The ratio T2/T1 is selected to be high enough so that in the programming of the MOS_Cap, gate dielectric 26D is broken down, while gate dielectric 24D remains not broken down. In accordance with some embodiments, the ratio T2/T1 is greater than about 1.5, and may be greater than about 2.0. Ratio T2/T1 may be between about 1.5 and about 2.5. This ratio range ensures that when gate dielectric 26D is broken down, gate dielectric 24D remains not broken down with adequate but not excess margin. In accordance with some embodiments of the present disclosure, gate dielectric 26D is formed simultaneously as, and hence having the same thickness as, core transistors (not shown) in the same chip, and gate dielectric 24D is formed simultaneously as, and hence having the same thickness as, Input/output (10) transistors (not shown) in the same chip.
It is further observed that the MOS_Cap and the R_Mos are formed in a same P_well 23, which also extends throughout the anti-fuse cell array 120, as shown in
Referring back to
Cross-sectional views are taken from
The cross-sectional view obtained from the plane containing line 11A-11A in
Referring to
Table 1 illustrates an example of the voltages applied to the selected and unselected word-lines, and the voltages applied to the selected and unselected bit-lines during program and read operations. It is appreciated that the voltages provided in Table 1 are examples, and different voltage may be used.
As shown in Table 1, in a program operation, the selected word-line is applied with a voltage between about 3V and about 5V, the unselected word line is applied with a voltage of 0V. The voltage of 3V˜5V is high enough to break down the gate dielectric of the MOS_Cap in the selected cell, but not high enough to break down (damage) the gate dielectric of the R_MOS in the selected cell. The selected bit-line is applied with a voltage of 0V, and the unselected bit-line is applied with a voltage equal to about a half (about 1.5V to about 2.5V) of the voltage applied on the selected word-line. In a read operation, the selected word-line is applied with a voltage between about 0.8V and about 1.8V, the unselected word line is applied with a voltage of 0V. The selected bit-line is pre-charged to a selected voltage (such as 0V), and the unselected bit-line is applied with a voltage of 0V or another predetermined voltage, or kept floating. The voltage of about 0.8V˜1.8V is low enough not to break any gate dielectric in the respective anti-fuse cell. The voltages in Table 1 are provided by a power source(s) (not shown) connected to the word-lines and bit-lines.
In a program operation, as shown in
Referring again to
For similar reasons, the cells in remaining anti-fuse cells are not applied with voltage that is high enough to cause breakdown, and hence no breakdown occurs.
The embodiments of the present disclosure have some advantageous features. The reading device R_MOS and the programming capacitor (MOS_Cap or Pro_MOS) in a same anti-fuse cell are connected to the same word line. Accordingly, the structure and the operation of the anti-fuses are simplified. The sizes of the respective macro are also reduced. A single word-line control circuit may be used. Furthermore, the reading device R_MOS and the programming capacitor in the same anti-fuse cell share a same active region and a same P_well region, and hence the size of the anti-fuse cell is reduced.
In accordance with some embodiments of the present disclosure, a structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.
In accordance with some embodiments of the present disclosure, a structure includes a word-line extending in a first direction, a bit-line extending in a second direction perpendicular to the first direction, an active region extending in the second direction, and an anti-fuse cell. The anti-fuse cell includes a reading device and a programming device. The reading device includes a first gate dielectric having a first thickness on sidewalls and a top surface of the active region, a first gate electrode over the first gate dielectric and extending in the first direction, wherein the first gate electrode is connected to the word-line, a drain region connected to the bit-line, and a source region. The drain region and the source region are on opposite sides of the first gate electrode. The programming device includes a second gate dielectric on a sidewall and a top surface of the active region, a second gate electrode over the second gate dielectric and extending in the first direction, a source/drain region connected to the first source region, and a channel region overlapped by the second gate electrode. The second gate electrode is connected to the word-line. The channel region and the source/drain region are of a same conductivity type. The second gate dielectric has a second thickness smaller than the first thickness.
In accordance with some embodiments of the present disclosure, a method includes programming an array, wherein the array has a plurality of anti-fuse cells arranged as rows and columns. Each of the plurality of anti-fuse cells has a reading device and a programming device. The programming includes applying a first voltage to a word-line connected to a first gate of the reading device and a second gate of the programming device, wherein the reading device and the programming device are in a selected cell. The programming further includes applying a second voltage to a drain region of the reading device. The first voltage and the second voltage in combination result in breakdown of a first gate dielectric in the programming device. A second gate dielectric in the reading device remains not broken down by the first voltage and the second voltage.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A structure comprising:
- a word-line;
- a bit-line; and
- an anti-fuse cell comprising: a reading device comprising: a first gate electrode connected to the word-line; a first gate dielectric underlying the first gate electrode, wherein the first gate dielectric has a first thickness; a drain region connected to the bit-line; and a source region, wherein the drain region and the source region are on opposite sides of the first gate electrode; and a programming device comprising: a second gate electrode connected to the word-line; a second gate dielectric underlying the second gate electrode, wherein the second gate dielectric has a second thickness smaller than the first thickness; and a first source/drain region connected to the source region: and a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the second gate electrode.
2. The structure of claim 1, wherein the drain region of the reading device, the source region of the reading device, and the first source/drain region of the programming device are in a same p-well region.
3. The structure of claim 1, wherein a channel region directly underlying the second gate electrode is doped as a same conductivity type as the first source/drain region of the programming device.
4. The structure of claim 1, wherein the first source/drain region of the programming device and a channel region directly underlying the second gate electrode are doped to different conductivity types.
5. The structure of claim 1, wherein the reading device is a Fin Field-Effect Transistor (FinFET), and the programming device is a fin-based device.
6. The structure of claim 1, wherein the first gate dielectric and the second gate dielectric are formed on a same semiconductor active region.
7. The structure of claim 1, wherein the programming device has no second source/drain region.
8. A structure comprising:
- a word-line extending in a first direction;
- a bit-line extending in a second direction perpendicular to the first direction;
- an active region extending in the second direction;
- an anti-fuse cell comprising: a reading device comprising: a first gate dielectric having a first thickness on sidewalls and a top surface of the active region; a first gate electrode over the first gate dielectric and extending in the first direction, wherein the first gate electrode is connected to the word-line; a drain region connected to the bit-line; and a source region, wherein the drain region and the source region are on opposite sides of the first gate electrode; and a programming device comprising: a second gate dielectric on a sidewall and a top surface of the active region, wherein the second gate dielectric has a second thickness smaller than the first thickness; a second gate electrode over the second gate dielectric and extending in the first direction, wherein the second gate electrode is connected to the word-line; a source/drain region connected to the source region; and a channel region overlapped by the second gate electrode, wherein the channel region and the source/drain region are of a same conductivity type.
9. The structure of claim 8 further comprising a connection module connecting the first gate electrode of the reading device and the second gate electrode of the programming device to the word-line.
10. The structure of claim 8, wherein the active region has an end overlapped by the second gate electrode of the programming device, and the active region is on a first side of the second gate electrode of the programming device, and not on a second side of the second gate electrode of the programming device, with the first side and the second side being opposite sides.
11. The structure of claim 8, wherein the active region has portions on opposite sides of the second gate electrode of the programming device.
12. The structure of claim 8, wherein the first thickness is greater than the second thickness by greater than about 50 percent.
13. The structure of claim 8 further comprising a dummy gate electrode, wherein an end of the active region is overlapped by the dummy gate electrode.
14. The structure of claim 8 further comprising a circuit, wherein the circuit is configured to:
- apply a first voltage to the word-line; and
- apply a second voltage to a drain region of the reading device, wherein the first voltage and the second voltage in combination result in breakdown of the second gate dielectric, and the first gate dielectric is not broken down by the first voltage and the second voltage.
15. A method comprising:
- programming an array, wherein the array comprises a plurality of anti-fuse cells arranged as rows and columns, and each of the plurality of anti-fuse cells comprises a reading device and a programming device, the programming comprising: applying a first voltage to a word-line connected to a first gate of the reading device and a second gate of the programming device, wherein the reading device and the programming device are in a selected cell; and applying a second voltage to a drain region of the reading device, wherein the first voltage and the second voltage in combination result in breakdown of a first gate dielectric in the programming device, and a second gate dielectric in the reading device remains not broken down by the first voltage and the second voltage; and
- reading a cell in the array, wherein the reading comprises: applying a third voltage to the word-line, wherein the third voltage is configured not to break any gate dielectric in the array; and sensing a voltage on a bit-line, wherein the bit-line is connected to the drain region of the reading device.
16. The method of claim 15, wherein after the first gate dielectric is broken down, the second gate and a source region of the reading device is resistively connected.
17. The method of claim 15, wherein during the programming, unselected cells connected to unselected word-lines in the array are applied with a voltage of 0V, and bit-lines connected to unselected cells connected to the word-line are applied with a voltage equal to about a half of the first voltage.
18. The method of claim 15, wherein the programming device is a partial MOS capacitor.
19. The method of claim 15, wherein the programming device is a three-terminal MOS capacitor.
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Type: Grant
Filed: Jan 22, 2016
Date of Patent: Jul 3, 2018
Patent Publication Number: 20170154686
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Jhon Jhy Liaw (Zhudong Township), Shien-Yang Wu (Jhudong Town)
Primary Examiner: David Lam
Application Number: 15/004,329
International Classification: G11C 17/00 (20060101); G11C 17/18 (20060101); H01L 23/525 (20060101); H01L 23/528 (20060101); H01L 29/78 (20060101); H01L 29/94 (20060101); G11C 17/16 (20060101); H01L 27/112 (20060101);