Method of fabricating non-volatile memory device array
A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal.
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This application claims priority to U.S. Provisional Application Ser. No. 62/338,604, filed May 19, 2016, which is herein incorporated by reference.
BACKGROUNDComputers and many other electronic devices require information storage system that handles and processes data. Some information is stored in volatile memory that is lost when power is removed. While information stored in a hard disk drive, CD-ROM or the like is retained for a significant time in the absence of power. This long-term storage is typically high in capacity but relatively slow in speed. Non-volatile memory system can be reprogrammed, read, and erased electronically, and are therefore suitable for storing audio data in digital players and pictures in digital cameras.
Memory device manufacturing has reached a new generation. One such development includes volatile and non-volatile memory device upgrade. Crucial factors, for example, compactness, efficiency, reliability, low power operation, long life, and low price, are to be retained in a successor. Flash memory is a common non-volatile memory. A typical flash memory cell includes a floating gate for each bit or binary element of information stored. In addition, a series of transistors are required to retrieve specific memory bits or words. The physical configuration of a memory cell is therefore not trivial, because tunnelling of electrons onto and off the floating gate in a non-volatile memory can have great impact on the memory cell capacity.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A large number of computer systems and electronic devices store information in the fashion of non-volatile memory. Information stored in non-volatile memories can be retained after power is cut from the device and therefore be accessed for read and process.
A typical non-volatile memory device includes a field effect transistor on a silicon substrate. Data are stored by electrical charge in a separate gate electrode, known as a floating gate. Changing the threshold voltage of the field effect transistor through the electrical charge over the channel region of the transistor allows data storage. For example, in an n-channel enhancement device, a large number of electrons in a floating gate electrode create a high threshold voltage in the field effect transistor. When the control gate is grounded, current does not flow through the transistor, and this is defined as a logic 0 state. A reduction in the number of electrons creates a low threshold voltage. In this condition, when the control gate is grounded, current flows through the field effect transistor, and this is defined as a logic 1 state.
Flash electrically erasable programmable read only memory (EEPROM) is a common type of non-volatile memory device. The term “flash” was named in part because a flash operation is used to erase the content of a block of data simultaneously with electrical pulses.
An array of nanocrystal floating gates for non-volatile memory array retains data in similar mechanism. The charge storage nanocrystals are arranged in a crossbar array. Bars along a longitudinal direction are word lines, while bars perpendicular to the longitudinal bars are bit lines. Nanocrystals are sandwiched at the intersection where a word line and a bit line meet and capable of being charged or discharged with electrons as in any flash EEPROM memory. Data storage takes place when the threshold voltage is changed. In more detail, a charged nanocrystal yields a lower threshold voltage, whereas an uncharged nanocrystal yields a higher threshold voltage, and the shift between low and high threshold voltage indicates the switch of logic state 1 and 0. The nanocrystal floating gate can thus be used as a flash memory storage element. The nanocrystal floating gate exhibits flash storage capability and has higher density without the need of selector switches. The construction of nanocrystal floating gate allows self alignment between the word line and the bit line resembling NAND configuration. Method of fabricating the nanocrystal crossbar array and embodiments are elaborated hereinafter.
Turning now to
As set forth in operation 110 in
Conventional floating gate employs polysilicon. Silicon (Si) and germanium (Ge) are used in the silicon germanium layer 230 in order to achieve lower power consumption, faster access speed, and higher integration density over conventional metallic materials. The silicon germanium has a general formula, Si1-xGex, where x is a number smaller than 1 and larger than 0 (0<x<1). In some embodiments, the silicon germanium layer 230 has a formula of Si0.7Ge0.3. The silicon germanium layer 230 is disposed on the silicon layer 220 by, for example, epitaxy. Shape of the silicon germanium layer 230 resembles that of the silicon layer 220 in a strip (nanowire). A dimension of the silicon germanium layer 230 measures a thickness ranging from 5-25 nm and a width ranging from 3-15 nm. In some embodiments, the silicon germanium layer 230 has a thickness of 10 nm and a width of 5 nm. The silicon germanium layer 230 may have a different thickness from the silicon layer 220, while the width of the silicon layer 220 and the germanium layer 230 is of the same value. The thickness of the silicon germanium layer 230 is related to the formation of nanocrystals which will be described in more detail in the following text. In some embodiments, the silicon germanium layer 230 is the word line in a FinFET.
As set forth in operation 120, a gate oxide layer is formed over the silicon layer and the silicon germanium layer. This is illustrated in
As set forth in operation 130, a gate layer is deposited on the gate oxide layer. This is illustrated in
Attention is now invited to
As shown in
As set forth in operation 150, the silicon germanium layer is oxidized. This is illustrated in
The selection of materials is important in the formation of nanocrystal structure because the etching rate and the oxygen affinity have influence on the nanocrystal construction. The dimension of the nanocrystal and tunnel oxide layer are controlled by their starting material dimensions and can be fined tuned in the oxidation process. The germanium nanocrystal 235 has a diameter ranging from approximately 2 to 10 nm. In some embodiments, the germanium nanocrystal 235 has a diameter measures approximately 3-8 nm.
Attention is now invited to
Attention is now invited to
Attention is now invited to
Attention is now invited to
In some embodiments, the silicon layer 720 is doped in a different fashion. For example, as shown in
Turning now to
As set forth in operation 810, a channel region is formed on a wafer. Source and drain regions (not shown) are formed to define the channel region 915 and a pair of insulating structure is disposed along the elongated channel region 915. This is illustrated in
Still referring to
As set forth in operation 830, a gate oxide layer is formed over the fin 903. Please refer to
Turning now to
Referring to
The silicon layer 920 of the fin 903 remains intact in the patterning process because of the difference in etching rate. The materials used as the fin 903 are therefore important due to process criteria and design requirement. More specifically, the fin 903 includes layers of materials that exhibit significantly different etching rate against the same etching agent. As set forth in operation 860, the fin is oxidized. This is illustrated in
The method of fabricating non-volatile nanocrystal memory array allows nanocrystal self-alignment between the gate (word line) and the nanowire (bit line). The selection of materials is important because the etching rate and oxidation affinity play a pivotal role in the formation of nanocrystal. In addition, the dimension of the nanocrystal may be tuned according to the thickness of the starting material. The nanocrystal offers flash storage capability in the switch between 0 and 1 logic state. Given a fin pitch and a gate pitch both measuring of about 10 nm, the crossbar array of nanocrystal memory device has approximately a density of 10 Gb/mm2 without the need of selector switches. The non-volatile memory device array satisfies low power consumption, fast access speed, and high integration density to a significant extent.
In some embodiments, the method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized.
In some embodiments, the method of fabricating nanocrystal memory device includes, forming a channel region on a wafer. Next, a fin is formed in the channel region. Following that, a gate oxide layer is formed over the fin. A gate layer is then deposited over the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the fin are patterned. Finally, the fin is oxidized to form nanocrystals.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method comprising:
- stacking a silicon layer and a silicon germanium layer above a wafer such that the silicon germanium layer is above the silicon layer;
- forming a gate oxide layer over the silicon layer and the silicon germanium layer;
- depositing a gate layer on the gate oxide layer;
- patterning the gate layer, the gate oxide layer, and the silicon germanium layer; and
- after forming the gate oxide layer, oxidizing the silicon germanium layer to form a nanocrystal in the silicon germanium layer.
2. The method according to claim 1, wherein stacking the silicon layer and the silicon germanium layer above the wafer further comprises:
- depositing a bottom silicon layer on the wafer; and
- depositing the silicon layer on the bottom silicon layer.
3. The method according to claim 1, wherein oxidizing the silicon germanium layer further comprises:
- forming the nanocrystal in between the gate layer and the silicon layer; and
- forming a tunnel oxide layer in between the nanocrystal and the silicon layer.
4. The method according to claim 1, wherein the wafer is a silicon on insulator wafer.
5. The method according to claim 1, further comprising:
- depositing the wafer on an existing circuit layer;
- forming an insulator on the wafer; and
- depositing the silicon layer and the silicon germanium layer on the insulator.
6. The method according to claim 5, wherein the silicon layer and the silicon germanium layer are polycrystalline.
7. The method according to claim 6, further comprising:
- treating the silicon layer to form at least one doped region therein.
8. The method according to claim 3, wherein a diameter of the nanocrystal ranges between 2 and 10 nm.
9. The method according to claim 1, wherein patterning the gate layer, the gate oxide layer, and the silicon germanium layer further comprises:
- removing portions of the gate layer to form gaps, wherein the gap ranges between 6 and 30 nm.
10. A method comprising:
- forming a channel region on a wafer;
- forming a fin in the channel region;
- forming a gate oxide layer over the fin;
- depositing a gate layer over the gate oxide layer;
- patterning the gate layer, the gate oxide layer, and the fin; and
- oxidizing the fin to form a nanocrystal above a top surface of the channel region.
11. The method according to claim 10, wherein the fin includes a silicon layer and a silicon germanium layer over the silicon layer.
12. The method according to claim 11, wherein oxidizing the fin further comprises:
- oxidizing the silicon germanium layer to form the nanocrystal in between the gate layer and the silicon layer.
13. The method according to claim 12, wherein a diameter of the nanocrystal ranges between 2 and 10 nm.
14. The method according to claim 10, wherein forming the channel region on the wafer further comprises:
- forming a source/drain region defining the channel region; and
- forming insulating structures flanking the channel region.
15. The method according to claim 10, wherein forming the channel region on the wafer further comprises:
- depositing a bottom silicon layer in the channel region.
16. The method according to claim 10, wherein patterning the gate layer, the gate oxide layer, and the fin further comprises:
- removing portions of the gate layer to form gaps, wherein the gap ranges between 6 and 30 nm.
17. The method according to claim 10, wherein the wafer is a silicon on insulator wafer.
18. A method comprising:
- forming a plurality of first strips on a wafer and arranged in a first direction;
- forming a plurality of second strips that include a different material than the first strips on the first strips and that are arranged in the first direction;
- forming a gate oxide layer on the first and second strips;
- depositing a gate layer on the gate oxide layer;
- patterning the gate layer, the gate oxide layer, and the second strips such that the gate layer is arranged on a sidewall of the second strips; and
- after depositing the gate layer, oxidizing the patterned second strips.
19. The method according to claim 18, wherein the plurality of first strips has a dopant and the gate layer is intrinsic.
20. The method according to claim 18, wherein the first strips include silicon and the second strips include silicon germanium.
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Type: Grant
Filed: Jun 29, 2016
Date of Patent: Dec 25, 2018
Patent Publication Number: 20170338237
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Hsinchu)
Inventors: Jean-Pierre Colinge (Hsinchu), Carlos H. Diaz (Mountain View, CA)
Primary Examiner: Joseph Galvin, III
Application Number: 15/196,126
International Classification: H01L 21/02 (20060101); H01L 29/66 (20060101); H01L 21/28 (20060101); H01L 29/423 (20060101); H01L 29/788 (20060101); H01L 27/11524 (20170101);