Reduced gate charge field-effect transistor
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift region, and source diffusions formed in the body. The source diffusions are adjacent a gate trench extending through the body into the drift region and having a dielectric liner and a gate electrode situated therein. The dielectric liner includes an upper segment and a lower segment, the upper segment extending to at least a depth of the source diffusions and being significantly thicker than the lower segment.
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Vertical power transistors, such as group IV based trench type field-effect transistors (trench FETS), are used in a variety of applications. For example, silicon based trench metal-oxide-semiconductor FETS (trench MOSFETs) may be used to implement a power converter, such as a synchronous rectifier, or a direct current (DC) to DC power converter.
For many trench MOSFET applications in which high switching speeds are necessary or desirable, it is advantageous to reduce gate charge so as to reduce switching loss. In addition, as the electronic devices and systems utilizing power MOSFETs are continually reduced in size, there is a corresponding need to reduce the size of the MOSFETs themselves. However, the resulting reduction in cell pitch and increased power density tends to undesirably increase gate charge in conventional trench MOSFET structures.
SUMMARYThe present disclosure is directed to a reduced gate charge field-effect transistor (FET), substantially as shown in and/or described in connection with at least one of the figures, and as set forth in the claims.
The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a mariner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
With respect to
Referring to flowchart 100, in
As further shown by structure 202 in
Substrate 220 may be implemented as a group IV based substrate, such as a silicon (Si) substrate or a silicon carbide (SiC) substrate, for example. Moreover, in some implementations, substrate 220 may include N type drift region 224 and P type body 230 formed in an epitaxial silicon layer of substrate 220. Formation of such an epitaxial silicon layer may be performed by any suitable method, as known in the art, such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE), for example. More generally, however, N type drift region 224 and P type body 230 may be formed in any suitable elemental or compound semiconductor layer included in substrate 220.
Thus, in other implementations, N type drift region 224 and P type body 230 need not be formed through epitaxial growth, and/or need not be formed of silicon. For example, in one alternative implementation, N type drift region 224 and P type body 230 can be formed in a float zone silicon layer of substrate 220. In other implementations, N type drift region 224 and P type body 230 can be formed in either a strained or unstrained germanium layer formed as part of substrate 220.
P type body 230 including lower doped P type body region 232, and highly doped P type body contacts 238 may be formed by implantation and thermal diffusion. For example, boron (B) dopants may be implanted into substrate 220 and diffused to form P type body 230 including lower doped P type body region 232, and highly doped P type body contacts 238. By analogy, highly doped N type source diffusions 236 may be formed by implantation and thermal diffusion of a suitable N type dopant in substrate 220. Such a suitable N type dopant may include arsenic (As) or phosphorous (P), for example.
Gate electrode 244 may be formed using any electrically conductive material typically utilized in the art. For example, gate electrode 244 may be formed of doped polysilicon or metal. Dielectric liner 242 insulating gate electrodes 240 from highly doped N type source diffusions 236, P type body 230, and N type drift region 224 may be formed using any material and any technique typically employed in the art. For example, dielectric liner 242 may be formed of silicon dioxide (SiO2), and may be deposited or thermally grown to produce dielectric liner 242.
It is noted that although the implementation shown in
It is further noted that in the interests of ease and conciseness of description, the present inventive principles will in some instances be described by reference to specific implementations of a silicon based vertical power FET. However, it is emphasized that such implementations are merely exemplary, and the inventive principles disclosed herein are broadly applicable for use with a wide variety of device types.
Moving to
It is noted that predetermined depth 254 and depth 234 of lower doped e body region 232 will typically be substantially equal to one another in substrate 220. Predetermined depth 254 and depth 234 of lower doped P type body region 232 are shown as different depths in
Referring now to
As further shown by structure 206, upper segment 242b of dielectric liner 242 having upper width 216 extends to predetermined depth 254, which is at least as deep as highly doped N type source diffusions 236 and may extend below highly doped N type source diffusions 236, as shown by depth 234. However, it is noted that depth 234 terminates within P type body 230. As a result, upper segment 242b of dielectric liner 242 is entirely situated above N type drift region 224.
It is also noted that the doping concentration of P type body 230 can be reduced adjacent upper segment 242b of dielectric liner 242. As a result, P type body 230 may include lower doped P type body region 232 extending to a depth 234, which corresponds to predetermined depth 254 and extends below top surface 226b of substrate 220 to at least the depth of highly doped N type source diffusions 236. However, and as discussed above, depth 234 may extend below below highly doped N type source diffusions 236.
Upper thickness 216 of dielectric liner 242 may be a conformally deposited or grown dielectric, such as SiO2, and may be formed on exposed portions of dielectric liner 242. In some implementations, upper thickness 216 of dielectric liner 242 may be increased using the same dielectric material used to form thickness 212 of dielectric liner 242, shown in
As stated above, upper segment 242b of dielectric liner 242, having thickness 216, is significantly thicker than lower segment 242a of dielectric liner 242, having thickness 212. For example, upper segment 242b may be from approximately 1.5 to approximately 2.5 times as thick as lower segment 242a, such as approximately twice as thick as lower segment 242a.
According to the exemplary implementation shown by
Continuing to
Formation of thick upper segment 244b of dielectric liner 242 extending at least to the depth of highly doped N type source diffusions 236 but less than the depth of N type drift region 224 reduces gate charge and improves switching efficiency. Moreover, because lower doped P type body region 232 may be localized so as to be situated adjacent and adjoin, thick upper segments 244b, the present solution for reducing gate charge can substantially minimize the affect of lower doped P type body region 232 on drain induced barrier lowering (DIBL). As a result, structure 208, in
Referring to
In contrast to reduced gate charge FET structure 208, in
From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.
Claims
1. A reduced gate charge field-effect transistor (FET) comprising:
- a drift region situated over a drain, a body situated over said drift region, and source diffusions in said body, said source diffusions being adjacent a gate trench;
- said gate trench extending through said body into said drift region and having a dielectric liner and a gate electrode situated therein;
- wherein said dielectric liner comprises an upper segment and a lower segment, said upper segment extending to at least a depth of said source diffusions, said upper segment being significantly thicker than said lower segment,
- wherein said upper segment of said dielectric liner extends below said depth of said source diffusions.
2. The reduced gate charge FET of claim 1, wherein said upper segment of said dielectric liner adjoins said source diffusions.
3. The reduced gate charge FET of claim 1, wherein said upper segment of said dielectric liner is situated above said drift region.
4. The reduced gate charge FET of claim 1, wherein said body comprises a lower-doped body region adjacent said upper segment of said dielectric liner and a higher-doped bod region adjacent said lower segment of said dielectric liner.
5. The reduced gate charge FET of claim 1, wherein said gate electrode is significantly narrower adjacent said upper segment of said dielectric liner.
6. The reduced gate charge FET of claim 1, wherein said upper segment of said dielectric liner is approximately twice as thick as said lower segment.
7. The reduced gate charge FET of claim 1, wherein said gate electrode is recessed within said gate trench, adjacent said upper segment of said dielectric lner.
8. The reduced gate charge FET of claim 1, wherein said reduced gate charge FET is an n-channel FET.
9. The reduced gate charge FET of claim 1, wherein said reduced gate charge FET is a p-channel FET.
10. The reduced gate charge FET of claim 1, wherein said upper segment and said lower segment are formed from the same dielectric material.
11. The reduced gate charge FET of claim 1, wherein an increased thickness of said upper segment over said lower segment is provided by a different dielectric material than that which forms said lower segment.
12. The reduced gate charge FET of claim 1, wherein said lower segment and an outer part of said upper segment comprise silicon dioxide, wherein an inner part of said upper segment comprises silicon nitride, and wherein an increased thickness of said upper segment over said lower segment is provided by said silicon nitride.
13. The reduced gate charge FET of claim 1, wherein said upper segment of said dielectric liner is approximately 1.5 to approximately 2.5 times as thick as said lower segment.
14. The reduced gate charge FET of claim 1, wherein said body region comprises a lower-doped body region and highly doped body contacts in said lower-doped body region.
15. The reduced gate charge FET of claim 14, wherein said upper segment of said dielectric liner extends to a depth of said lower-doped body region.
16. The reduced gate charge FET of claim 1, wherein a channel region in said body extends from said source diffusions to said lower segment of said dielectric liner along said upper segment.
17. A transistor, comprising:
- a drift region over a drain;
- a body over said drift region;
- a source diffusion in said body;
- a trench extending through said body into said drift region; and
- a dielectric liner and an electrode situated in said trench,
- wherein said dielectric liner comprises an upper segment and a lower segment,
- wherein said upper segment is situated entirely above said drift region,
- wherein said upper segment is significantly thicker than said lower segment,
- wherein said body comprises a lower-doped body region adjacent said upper segment of said dielectric liner and a higher-doped body region adjacent said lower segment of said dielectric liner.
18. The transistor of claim 17, wherein said upper segment of said dielectric liner is approximately 1.5 to approximately 2.5 times as thick as said lower segment.
19. A transistor, comprising:
- a drift region over a drain;
- a body over said drift region;
- a source diffusion in said body;
- a gate trench extending through said body into said drift region; and
- a dielectric liner and a gate electrode situated in said gate trench,
- wherein said dielectric liner comprises an upper segment and a lower segment,
- wherein said upper segment is significantly thicker than said lower segment,
- wherein said gate electrode is spaced apart from said source diffusion by said upper segment of said dielectric liner,
- wherein a channel region in said body extends from said source diffusions to said lower segment of said dielectric liner vertically along said upper segment.
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Type: Grant
Filed: Aug 17, 2017
Date of Patent: Feb 12, 2019
Patent Publication Number: 20170345924
Assignee: Infineon Technologies Austria AG (Villach)
Inventors: David Laforet (Villach), Li Juin Yip (Villach), Cedric Ouvrard (Villach)
Primary Examiner: Sonya D. McCall-Shepard
Application Number: 15/679,577