Multi-level Metallization Patents (Class 257/211)
  • Patent number: 10629512
    Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
  • Patent number: 10601525
    Abstract: A system incorporating a power distribution for functional circuit blocks can include a functional circuit block comprising two or more sub-circuits; a power line comprising at least two segments, a first sub-circuit of the two or more sub-circuits being coupled to a first segment of the at least two segments, and a second sub-circuit of the two or more sub-circuits being coupled to a second segment of the at least two segments; and at least one power delivery circuit (PDC) coupled to the power line at a location to create an electromagnetic flux on two adjacent segments of the at least two segments that is in opposite directions. The PDCs can be arranged coupled to the power line with a number and at locations optimized for mitigating electromagnetic emissions on the power line.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 24, 2020
    Assignee: ARM LIMITED
    Inventors: Mikael Yves Marie Rien, Subbayya Chowdary Yanamadala
  • Patent number: 10593622
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10553744
    Abstract: A light emitting device can include a substrate including first and second surfaces, the substrate having a thickness of less than 350 micrometers; a reflective layer on the second surface of the substrate; a light emitting structure on the first surface of the substrate and including first and second semiconductor layers with an active layer therebetween, the second semiconductor layer includes an aluminum-gallium-nitride layer, and the active layer includes aluminum and indium and has a multiple quantum well layer; a transparent conductive layer disposed on the second semiconductor layer and including an indium-tin-oxide; a first electrode on the first semiconductor layer and including multiple layers; a second electrode on the transparent conductive layer and including multiple layers; first and second pads on the first and second electrodes, respectively, in which the second pad includes the same material as the first pad and has a thickness of more than 500 nanometers.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: February 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10537019
    Abstract: Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 14, 2020
    Assignee: NXP USA, Inc.
    Inventors: Tingdong Zhou, Twila Jo Eichman, Stanley Andrew Cejka, James S. Golab, Chee Seng Foong
  • Patent number: 10535576
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 14, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Patent number: 10446555
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu
  • Patent number: 10424577
    Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhak Lee, Sang-Yeop Baeck, JaeSeung Choi, Hyunsu Choi, SangShin Han
  • Patent number: 10418551
    Abstract: A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 10410934
    Abstract: Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Nanae Yokoyama, Ryota Suzuki, Makoto Sato
  • Patent number: 10396027
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10361155
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10361320
    Abstract: A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and is within 100 ?m at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 23, 2019
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yoshihide Komatsu
  • Patent number: 10355050
    Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul-ji Song, Jung-hoon Park, Sung-ho Eun
  • Patent number: 10347638
    Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan T. Doebler
  • Patent number: 10332792
    Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christopher J. Gambee
  • Patent number: 10304849
    Abstract: A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ryosuke Sawabe, Masaru Kito
  • Patent number: 10269635
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Patent number: 10269715
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10199389
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
  • Patent number: 10199290
    Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 5, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10158071
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 10147679
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10115899
    Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line by selectively forming a conductive oxide material layer adjacent the word line, and forming a semiconductor material layer adjacent the bit line, and forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Yusuke Yoshida, Tomohiro Uno, Tomoyuki Obu, Takeki Ninomiya, Toshihiro Iizuka
  • Patent number: 10083636
    Abstract: Provided is a flexible display device including a flexible display panel having a substrate and an organic electroluminescent member disposed on the substrate, a window member disposed on the flexible display panel, and a protection member disposed under the flexible display panel, wherein the protection member includes a metal layer disposed under the substrate, a cushion layer disposed under the metal layer, and a planarization layer and disposed between the metal layer and the cushion layer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jiwon Han
  • Patent number: 10079247
    Abstract: Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The stacked structure includes at least one interlayer insulating layer and at least one sacrificial layer alternately stacked with the at least one interlayer insulating layer. A first trench is formed to extend through the stacked structure and to expose the conductive substrate structure. A first gate electrode layer, a dielectric structure, and a channel layer are formed on a side wall of the first trench, the dielectric structure including a ferroelectric layer. At least one recess is formed to expose a side wall of the first gate electrode layer by removing the at least one sacrificial layer. At least one second gate electrode layer is formed by filling the at least one recess with a conductive layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 18, 2018
    Assignee: SK HYNIX INC.
    Inventor: Joong Sik Kim
  • Patent number: 10056369
    Abstract: A method includes forming a plurality of openings extending through a semiconductor layer, through a buried insulating layer, and into a substrate material in a second device region of a semiconductor device while covering a first device region of the semiconductor device. An insulating material is formed on sidewalls and on a bottom face of each of the plurality of openings, and a first capacitor electrode is formed in each of the plurality of openings in the presence of the insulating material, wherein each of the first capacitor electrodes includes a conductive material and partially fills a respective one of the plurality of openings.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Frank Jakubowski
  • Patent number: 10056404
    Abstract: The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeduk Lee, Youngwoo Park
  • Patent number: 10043966
    Abstract: A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hoon Bak, Kyung-tae Nam, Yong-jae Kim, Da-hye Shin
  • Patent number: 10020257
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 9991204
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9964587
    Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Kuo Wang, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 9941205
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 9929041
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the foundation layer, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The plurality of electrode layers of the second stacked portion has a plurality of terrace portions arranged in a staircase configuration by forming a level difference in a first direction. The insulating layer provides on the plurality of terrace portions, the insulating layer includes silicon oxide as a major component. The insulating layer includes an upper layer portion and a lower layer portion. An oxygen composition ratio of the upper layer portion is lower than an oxygen composition ratio of the lower layer portion.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shunsuke Hazue
  • Patent number: 9915843
    Abstract: In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 9893074
    Abstract: A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Goo Lee, Young Woo Park
  • Patent number: 9881935
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 30, 2018
    Assignee: SK Hynix Inc.
    Inventor: Kwang-Seok Oh
  • Patent number: 9831924
    Abstract: An apparatus including a board, an inductor that is provided on the board, a guard ring that includes a first guard ring part provided to be adjacent to a circumference of the inductor and a second guard ring part provided to be adjacent to an outer side of the first guard ring part, in which one end of the second guard ring part is connected to one end of the first guard ring part, and a first power supply that is connected to another end of the first guard ring part and another end of the second guard ring part.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Xihua Lin
  • Patent number: 9825123
    Abstract: A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 21, 2017
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Tatsuji Nagaoka, Hiroki Miyake, Yukihiko Watanabe, Sachiko Aoi, Atsuya Akiba
  • Patent number: 9818752
    Abstract: A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. Tao, Jacklyn Chang, Kuoyuan (Peter) Hsu, Yukit Tang
  • Patent number: 9711454
    Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Fang, Jung-Chih Tsao, Yao-Hsiang Liang, Yu-Ku Lin
  • Patent number: 9704783
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Patent number: 9672917
    Abstract: Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiying Costa, Henry Chien, Yao-Sheng Lee, Yanli Zhang
  • Patent number: 9666542
    Abstract: A wiring substrate is provided with a support substrate (31), an insulating layer (32), and a wiring layer (33). The support substrate (31) is formed with a hole (34) including an opening portion in one surface of the support substrate (31). The insulating layer (32) is formed on a surface of the support substrate (31) opposite to the one surface thereof including the opening portion. The wiring layer (33) includes a wiring pattern of a predetermined structure on the insulating layer (32). Further, an orthographic projection to be obtained when the wiring pattern is projected on a predetermined surface of the support substrate (31), and an orthographic projection to be obtained when the hole (34) is projected on the predetermined surface of the support substrate (31) include a shared portion.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 30, 2017
    Assignee: NEC CORPORATION
    Inventor: Junichi Tsuchida
  • Patent number: 9659997
    Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: May 23, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jong-Won Lee, Gianpaolo Spadini, Stephen W. Russell, Derchang Kau
  • Patent number: 9659998
    Abstract: An integrated circuit memory comprises an intermediate layer disposed between a plurality of bit lines in a bit line conductor layer and a plurality of word lines in a word line conductor layer. The intermediate layer includes a plurality of memory posts through an interlayer insulating structure. Each memory post has a memory element and an access element. The interlayer insulating structure includes higher thermal resistance at the level of the memory element than at the level of the access element.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 23, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 9653394
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • Patent number: 9646984
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
  • Patent number: 9536035
    Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Juhan Kim, Jongwook Kye, Mahbub Rashed
  • Patent number: 9536613
    Abstract: A semiconductor memory device may include a plurality of cell strings. Each of the cell strings may include at least one source selection transistor connected to a common source line, a plurality of memory cells connected to the common source line through the at least one source selection transistor. Each of the cell strings may include at least one source selection line connected to source selection transistors of the plurality of the cell strings. The semiconductor memory device may include peripheral circuit. The peripheral circuit may be configured to control the plurality of the cell strings. The peripheral circuit may be configured to perform a program on the source selection transistors connected to a selected source selection line by applying a program voltage to the selected source selection line among the at least one source selection line, and by applying a reference voltage to the common source line.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 3, 2017
    Assignee: SK HYNIX INC.
    Inventor: Hee Youl Lee