Multi-level Metallization Patents (Class 257/211)
  • Patent number: 11348918
    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyung Kim, Jinwoo Jeong, Jiwook Kwon, Raheel Azmat, Kwanyoung Chun
  • Patent number: 11335654
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Patent number: 11302695
    Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 11217496
    Abstract: A device and methods for forming the device is provided. The device includes a substrate and circuit elements thereon. The device further includes a metallization layer over the substrate. The metallization layer includes interconnects interconnecting the circuit elements. A test pad is disposed over an uppermost interconnect in the metallization layer. The test pad is coupled to one or more circuit elements via the interconnects. The test pad is configured for testing the one or more circuit elements. A crack stop protection seal surrounding the test pad is provided. The crack stop protection seal confines damage caused by probing at the test pad from propagating to an area beyond the crack stop protection seal.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 4, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ramasamy Chockalingam, Juan Boon Tan, Wanbing Yi
  • Patent number: 11211496
    Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xi-Zong Chen, Te-Chih Hsiung, Cha-Hsin Chao, Yi-Wei Chiu
  • Patent number: 11158368
    Abstract: A six transistor SRAM memory cell design is discussed. An SRAM memory cell includes criss-crossed transistors in cross-coupled inverters to achieve a more compact form factor and simplify fabrication.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: October 26, 2021
    Assignee: Coventor, Inc.
    Inventors: Benjamin Vincent, Joseph Ervin
  • Patent number: 11080229
    Abstract: A three-dimensional processor (3D-processor) for calculating mathematical functions in parallel, comprises a larger number (e.g. at least one thousand) of computing elements, with each computing element comprising at least one three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Even though each individual 3D-M cell is slower than a conventional two-dimensional memory (2D-M) cell, this deficiency in speed is offset by a significantly larger scale of parallelism.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: August 3, 2021
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventors: Guobiao Zhang, Chen Shen
  • Patent number: 11074957
    Abstract: A semiconductor device includes a period signal generation circuit and an interruption signal generation circuit. The period signal generation circuit generates a period signal in response to a refresh pulse and an end pulse. The interruption signal generation circuit generates an interruption signal for controlling an operation that an address is set as a target address, if the address having the same logic level combination as the target address is inputted while the period signal is enabled.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Jae Il Kim
  • Patent number: 11056661
    Abstract: The present invention provides a color conversion layer, a manufacturing method of the color conversion layer, and a display panel. The color conversion layer is used in a display panel having a direct surface light source. The color conversion layer includes a quantum dot film and a functional film. The functional film is arranged at one side of the quantum dot film facing the direct surface light source. A light wave emitted by the direct surface light source is transmitted through the functional film into the quantum dot film. A light wave excited by the quantum dot film is reflected into the quantum dot film through the functional film.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 6, 2021
    Inventors: Guiyang Zhang, Guowei Zha
  • Patent number: 11043451
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 11004985
    Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hun Lee, Dong Woo Kim, Dong Chan Suh, Sun Jung Kim
  • Patent number: 10978554
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang
  • Patent number: 10964820
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Jack T. Kavalieros
  • Patent number: 10952893
    Abstract: To provide a multilayer film for a disposable body warmer outer bag, and a disposable body warmer that are excellent in gas barrier property which inhibits permeation of oxygen gas, water vapor and the like, and that can allow swelling due to hydrogen gas generated during a storage period to be prevented. In a disposable body warmer outer bag formed from a multilayer film including a sealant layer 10 and a barrier layer 20, the sealant layer 10 and the barrier layer 20 serve as an inner surface and an outer surface of the outer bag, respectively. The sealant layer 10 includes a vapor-deposited layer 12 made by vapor-depositing a metal or metal oxide on at least one surface (upper portion in FIG. 1) of a thermal fusible resin substrate 11. The barrier layer 20 includes a polyvinylidene chloride layer 22 made by coating at least one surface (lower portion in FIG. 1) of a heat-resistant resin substrate 21 with polyvinylidene chloride.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 23, 2021
    Assignee: KOBAYASHI PHARMACEUTICAL CO., LTD.
    Inventors: Hiroyuki Inoue, Takayuki Miyazaki, Tsuyoshi Igaue, Yorikazu Kotani
  • Patent number: 10950635
    Abstract: A transistor device includes a plurality of drain fingers that are elongate in a first dimension, a plurality of source fingers that are elongate in the first dimension and interleaved with the plurality of drain fingers, one or more drain contact bars extending over a first set of the plurality of drain fingers and a first set of the plurality of source fingers in a second dimension that is orthogonal to the first dimension, and one or more source contact bars extending over a second set of the plurality of drain fingers and a second set of the plurality of source fingers in the second dimension.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 16, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Tzung-Yin Lee, Aniruddha B. Joshi, David Scott Whitefield, Maureen Rosenberg Brongo
  • Patent number: 10896913
    Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate. The semiconductor substrate includes a first surface. A first semiconductor layer is provided on a first region of the first surface. A first transistor is provided on the first semiconductor layer. A second semiconductor layer is provided on a second region of the first surface. A second transistor is provided on the second semiconductor layer. A stacked body is provided on a third region of the first surface. The stacked body includes a plurality of conductors and a plurality of memory pillars. A first insulator is provided between the first semiconductor layer and the second semiconductor layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: January 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takashi Fukushima, Junya Fujita, Toshiharu Nagumo
  • Patent number: 10861804
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Patent number: 10833061
    Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
  • Patent number: 10833069
    Abstract: Logic gate designs (e.g., NAND, NOR, Inverter) for stacked VTFET designs are provided. In one aspect, a logic gate device is provided. The logic gate device includes: at least one top vertical transport field-effect transistor (VTFET1) sharing a fin with at least one bottom VTFET (VTFET2); a power rail connected to a power contact of the logic gate device; and a ground rail, adjacent to the power rail, connected to a ground contact of the logic gate device. A method of forming a logic gate device is also provided.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita, Terence B. Hook
  • Patent number: 10833013
    Abstract: At integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: November 10, 2020
    Assignee: Monterey Research, LLC
    Inventors: Shenqing Fang, Connie Pin-Chin Wang, Wen Yu, Fei Wang
  • Patent number: 10804280
    Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Khaled Hasnat, Prashant Majhi, Deepak Thimmegowda
  • Patent number: 10790227
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first dielectric layer having a first region and a second regions at each of two sides of the first region on the semiconductor substrate; forming a first opening in the first region of the first dielectric layer and a second opening in each of the second regions of the first dielectric layer; forming a first interconnect member in the first opening; forming a second interconnect member with a top surface lower than a top surface of the first dielectric layer in each of the second openings; forming a second dielectric layer having a third opening with a bottom exposing a top surface of the first interconnect member on surfaces of the first interconnect member, second interconnect members and the first dielectric layer; and forming an interconnect structure in the third opening.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 29, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xing Hua Song
  • Patent number: 10777742
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10734515
    Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 4, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Katsumi Suzuki, Yukihiko Watanabe
  • Patent number: 10727230
    Abstract: An integrated semiconductor device includes a first semiconductor device, an ILD layer and a second semiconductor device. The first semiconductor device has a first transistor structure. The ILD layer is over the first semiconductor device and has a thickness in a range substantially from 10 nm to 100 nm. The second semiconductor device is over the ILD layer and has a 2D material layer as a channel layer of a second transistor structure thereof.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 10720493
    Abstract: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 21, 2020
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yuichi Takeuchi, Katsumi Suzuki, Yukihiko Watanabe
  • Patent number: 10672847
    Abstract: A display device includes: thin film transistors (TFTs) on a substrate, pixel electrodes (PEs) respectively connected to the TFTs, common electrode blocks (CEBs) on the substrate, each CEB forming an electric field with a respective PE, touch sensing lines (TSLs) respectively connected to the CEBs, a lower planarization layer (PL) between the TFTs and the TSLs, an upper PL between the TSLs and one of: the PEs and the CEBs, an upper protective film between the PEs and the CEBs, and pixel contact holes extending through the lower PL and the upper PL to expose respective drain electrodes of the TFTs, wherein a side surface of each of the lower PL and the upper PL, exposed through the pixel contact holes, contacts one of: the upper protective film and the PEs.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 2, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Hee Nam, Jung-Ho Bang, Jung-Sun Beak, Seong-Joo Lee
  • Patent number: 10629512
    Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
  • Patent number: 10601525
    Abstract: A system incorporating a power distribution for functional circuit blocks can include a functional circuit block comprising two or more sub-circuits; a power line comprising at least two segments, a first sub-circuit of the two or more sub-circuits being coupled to a first segment of the at least two segments, and a second sub-circuit of the two or more sub-circuits being coupled to a second segment of the at least two segments; and at least one power delivery circuit (PDC) coupled to the power line at a location to create an electromagnetic flux on two adjacent segments of the at least two segments that is in opposite directions. The PDCs can be arranged coupled to the power line with a number and at locations optimized for mitigating electromagnetic emissions on the power line.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 24, 2020
    Assignee: ARM LIMITED
    Inventors: Mikael Yves Marie Rien, Subbayya Chowdary Yanamadala
  • Patent number: 10593622
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10553744
    Abstract: A light emitting device can include a substrate including first and second surfaces, the substrate having a thickness of less than 350 micrometers; a reflective layer on the second surface of the substrate; a light emitting structure on the first surface of the substrate and including first and second semiconductor layers with an active layer therebetween, the second semiconductor layer includes an aluminum-gallium-nitride layer, and the active layer includes aluminum and indium and has a multiple quantum well layer; a transparent conductive layer disposed on the second semiconductor layer and including an indium-tin-oxide; a first electrode on the first semiconductor layer and including multiple layers; a second electrode on the transparent conductive layer and including multiple layers; first and second pads on the first and second electrodes, respectively, in which the second pad includes the same material as the first pad and has a thickness of more than 500 nanometers.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: February 4, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10537019
    Abstract: Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 14, 2020
    Assignee: NXP USA, Inc.
    Inventors: Tingdong Zhou, Twila Jo Eichman, Stanley Andrew Cejka, James S. Golab, Chee Seng Foong
  • Patent number: 10535576
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 14, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Patent number: 10446555
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu
  • Patent number: 10424577
    Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhak Lee, Sang-Yeop Baeck, JaeSeung Choi, Hyunsu Choi, SangShin Han
  • Patent number: 10418551
    Abstract: A semiconductor memory device of an embodiment includes a memory cell array. The memory cell array comprises: a semiconductor layer extending in a first direction; a plurality of conductive layers that face a side surface of the semiconductor layer and are stacked in the first direction; a variable resistance film provided at an intersection of the semiconductor layer and one of the conductive layers; a plurality of contact parts provided at ends of the plurality of conductive layers in a second direction intersecting the first direction, respectively; and a plurality of conductive parts that extend in the first direction and are connected to the plurality of contact parts, respectively. At least one of the plurality of contact parts includes a projection part projecting in the second direction.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 10410934
    Abstract: Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Nanae Yokoyama, Ryota Suzuki, Makoto Sato
  • Patent number: 10396027
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10361320
    Abstract: A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and is within 100 ?m at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 23, 2019
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Yoshihide Komatsu
  • Patent number: 10361155
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10355050
    Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seul-ji Song, Jung-hoon Park, Sung-ho Eun
  • Patent number: 10347638
    Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan T. Doebler
  • Patent number: 10332792
    Abstract: A method of forming conductive traces comprises forming a seed material over a surface of a substrate, forming a patterned mask material over the seed material to define trenches leaving portions of the seed material within the trenches exposed, and depositing a conductive material over the exposed seed material in the trenches to form conductive traces. At least a portion of the patterned mask material is removed, a barrier formed over side surfaces and upper surfaces of the conductive traces, and exposed portions of the seed material are removed. Conductive traces and structures incorporating conductive traces are also disclosed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christopher J. Gambee
  • Patent number: 10304849
    Abstract: A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ryosuke Sawabe, Masaru Kito
  • Patent number: 10269715
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Patent number: 10269635
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Patent number: 10199389
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Goo Lee, Jae-Duk Lee
  • Patent number: 10199290
    Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 5, 2019
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 10158071
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 10147679
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li