Semiconductor chip set with double-sided off-chip bonding structure
A semiconductor chip set with double-sided off-chip bonding structure in the disclosure comprises at least one first off-chip bonding structure formed above a first surface of the semiconductor chip set, and at least one second off-chip bonding structure formed above a second surface of the semiconductor chip set, wherein the first surface is opposite to the second surface and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump.
The present application is a non-provisional application claiming benefit from a US Provisional patent application bearing a Ser. No. 62/787,727 and filed Jan. 2, 2019, contents of which are incorporated herein for reference.
FIELD OF THE INVENTIONThe present invention is related to the field of a semiconductor technique, and more specifically, related to a semiconductor chip set with double-sided off-chip bonding structure.
BACKGROUND OF THE INVENTIONBecause of the rapid development of semiconductor manufacturing processes, circuit density in a semiconductor chip is increased, and circuitry contained in and functions provided by the semiconductor chips of a unit silicon area are therefore increased. With respect to a memory chip in terms of this trend, the data storage capacity per unit area of the memory is increased. However, a critical point of this rapid development trend has been reached and the density increment of components per unit area of the semiconductor chip during a unit time period is slowed down. In order to keep a high growth trend, many chip-stacking techniques are being developed and provided. However, the availability of the off-chip bonding points of the chips of a stacked semiconductor chip set is an issue. Moreover, the requirement of a low inductance value and a low capacitance value for the power and signal terminals respectively of each of the stacked semiconductor chips cannot be met at the same time with only the through-silicon via (TSV) of which the capacitance is usually high, or with only the bonding wires of which the inductance is usually high.
SUMMARY OF THE INVENTIONIn order to overcome the drawbacks described above, a semiconductor chip set and semiconductor chip used therein with double-sided off-chip bonding structure are provided in the disclosure. Off-chip bonding structures provided by the semiconductor chip set could be more than those provided by prior arts such that limitation on the amount of circuits in the semiconductor chip set due to the amount of the off-chip bonding structures is reduced, and the minimum inductance or capacitance values existed between the power/ground or signal terminals of each of the stacked semiconductor chips and the external power/ground or signal terminals of the semiconductor component in which the stacked semiconductor chips are packaged would be further decreased.
In one aspect, the present disclosure provides a semiconductor chip set with double-sided off-chip bonding structure, which is characterized in that at least one first off-chip bonding structure is formed above a first surface of the semiconductor chip set, at least one second off-chip bonding structure is formed above a second surface of the semiconductor chip set, the first surface is opposite to the second surface, and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire or micro bump.
In one embodiment, the chip circuitry is formed near the first surface and connected to the first off-chip bonding structure.
In one embodiment, the chip circuitry is formed near the first surface and connected to the second off-chip bonding structure through a through-silicon-via set penetrating the semiconductor chip set.
In one embodiment, the semiconductor chip set is a single semiconductor chip, the first surface and the second surface are opposite two surfaces of the single semiconductor chip, and the chip circuitry is formed near the first surface, connected to the first off-chip bonding structure and further connected to the second off-chip bonding structure through a through-silicon-via penetrating the single semiconductor chip.
In one embodiment, the semiconductor chip set further comprises a plurality of semiconductor chips stacked together, wherein the semiconductor chips comprise a first chip and a second chip, a plurality of third off-chip bonding structures are respectively formed above opposite two surfaces of the first chip and opposite two surfaces of the second chip, and the third off-chip bonding structures are used for connecting with circuitry or power terminals external to the stacked semiconductor chips.
In one embodiment, a first control circuit and a first operation circuit electrically connected to the first control circuit are formed in the first chip, a second control circuit and a second operation circuit electrically connected to the second control circuit are formed in the second chip, and the second control circuit is electrically connected to the first operation circuit through a through-silicon-via penetrating the first chip; wherein the first operation circuit is controlled by the first control circuit when the first control circuit is turned on, and the first operation circuit and the second operation circuit are controlled by the second control circuit at the same time when the first control circuit is turned off.
In one embodiment, the semiconductor chip set further comprises a plurality of memory chips stacked together.
In one aspect, the present disclosure provides a semiconductor chip with double-sided off-chip bonding structure, which is characterized in that the semiconductor chip comprises a first surface and a second surface opposite to the first surface, the first surface is adapted to be disposed with a chip circuitry, at least one first off-chip bonding structure is formed above the first surface, at least one second off-chip bonding structure is formed above the second surface, and, at least one of the at least one second off-chip bonding structure is connected to the chip circuitry through a through-silicon-via; wherein, at least one of the at least one first off-chip bonding structure is connected to a first power or a first signal external to the semiconductor chip and at least one of the at least one second off-chip bonding structure is connected to a second power or a second signal external to the semiconductor chip.
In one embodiment, the at least one of the at least one first off-chip bonding structure is connected to the first power or the first signal through a first bonding wire or a first micro bump, and the at least one of the at least one second off-chip bonding structure is connected to the second power or the second signal through a second bonding wire or a second micro bump.
In one aspect, the present disclosure provides a semiconductor chip set comprising a plurality of semiconductor chips, each of the semiconductor chips being as the semiconductor chip recited above, and the semiconductor chips are connected together through connecting a part or all of the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of one of the semiconductor chips to a part or all of the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of another one of the semiconductor chips; wherein, the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of any one of the semiconductor chips is adapted to be connected to receive power external to the semiconductor chip set or is adapted to be connected to communicate signals with elements external to the semiconductor chip set.
Because the off-chip bonding structures are formed above both the front-side (the side/surface near which the chip circuitry is formed) and the back-side (opposite to the front-side) of the semiconductor chip set, the off-chip bonding structures provided by the semiconductor chip or semiconductor chip set recited above could be more than those provided by prior arts. Therefore, limitation on the amount of circuits in the semiconductor chip set due to the amount of the off-chip bonding structures is reduced, and the minimum inductance/capacitance values existed between the power terminal of each of the stacked semiconductor chips and the external power/grounding terminals of the semiconductor component in which the stacked semiconductor chips are packaged would be further decreased.
In order to make the descriptions of the technique solutions of the embodiments of the present invention or the existed techniques be clearer, the drawings necessary for describing the embodiments or the existed techniques are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and, for those with ordinary skill in this field, other drawings can be obtained from the drawings described below without creative efforts.
The technical solutions in the embodiments of the present disclosure are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present application.
Please refer to
Each circuit module in the chip circuitry could be connected to the off-chip bonding structures 140 or 160, or each circuit module could be connected to the off-chip bonding structures 140 and 160 at the same time. Each circuit module could be directly connected to the off-chip bonding structures 140 or 160, or each circuit module could be electrically connected to the off-chip bonding structures 140 or 160 through the medium having electrical connecting property as shown in
Please refer to
The techniques described in the embodiments mentioned above can be adapted to a semiconductor chip set composed of only one semiconductor chip, and, furthermore, these techniques can be applied to a semiconductor chip set comprising a plurality of semiconductor chips stacked together in a way described in following embodiments.
Please refer to
In the embodiment, the off-chip bonding structures 424, 444 and 448 can be connected to an electrical connecting point external to the semiconductor chip set 40. For example, the off-chip bonding structure 424 is connected to an external bonding point through bonding wire 430, the off-chip bonding structure 444 is connected to an external bonding point through bonding wire 450, and the off-chip bonding structure 448 is connected to an external bonding point through a micro bump. Therefore, an amount of the off-chip bonding structures (i.e., the off-chip bonding structures for connecting to external bonding points) provided on the semiconductor chip set 40 is more than an amount of the off-chip bonding structures provided on the conventional semiconductor chip set. Besides, the off-chip bonding structure 444 are not formed once only the off-chip bonding structures on front-side and back-side of the semiconductor chip set are needed. For example, please refer to
In order to provide off-chip bonding structures above opposite two surfaces of the semiconductor chip set comprising at least two stacked semiconductor chips, off-chip bonding structures are provided above one surface of each of the two semiconductor chips farthest apart. For example, in the embodiment illustrated in
It is noted that, when the semiconductor chip set comprises at least two stacked semiconductor chips, the semiconductor chips can be stacked by any reasonable ways besides those shown in
Advantages are obtained by adopting the technique described above, i.e., electrically connecting the stacked semiconductor chips with the TSVs. Please refer to
In a specific embodiment, when the semiconductor chips 72 and 74 shown in
Furthermore, circuitry arrangement of an electronic apparatus is more flexible by using the semiconductor chip set with double-sided off-chip bonding structure provided by the present disclosure. For example, please refer to
In one embodiment, the specific structure of the semiconductor chip set 80 is formed by at least two stacked semiconductor chips similar to that illustrated in
It is noted that the plurality of the semiconductor chips in a semiconductor chip set can be integrated in other ways as shown in
It is noted that one or more circuit modules can be formed with each of the semiconductor chips 9000, 9100 and 9200, and these circuit modules may be electrically connected to the off-chip bonding structures. In order to make the drawings be simple and easily understood, only a part of the off-chip bonding structures and circuit modules are illustrated in
It is noted that, the off-chip bonding structures in the embodiments described above can be connected to circuits external to the semiconductor chip set by using bonding wires or micro bumps or any other mediums with appropriate types.
In summary, because the off-chip bonding structures are formed with the front-side (the side/surface near which the chip circuitry is formed) and the back-side (opposite to the front-side) of the semiconductor chip set, the off-chip bonding structures provided by the semiconductor chip or semiconductor chip set can be more than those provided by prior arts. Therefore, limitation of circuits in the semiconductor chip set due to the limitation of the number of off-chip bonding structures is reduced, and the minimum inductance/capacitance values existed between the power terminal of each of the stacked semiconductor chips and the external power/grounding terminals of the semiconductor component in which the stacked semiconductor chips are packaged would be further decreased. Furthermore, design of connections between the semiconductor chip sets is more flexible such that a volume of the whole electronic apparatus is probably decreased. It is understood that, while packaging the semiconductor chips as a packaged I.C. (Integrated Circuit), a substrate must be provided as a package substrate of the packaged I.C. to stack the semiconductor chips together. In the embodiment shown in
The foregoing contents are detailed description of the disclosure in conjunction with specific preferred embodiments and concrete embodiments of the disclosure are not limited to the description. For the person skilled in the art of the disclosure, without departing from the concept of the disclosure, simple deductions or substitutions can be made and should be included in the protection scope of the application.
Claims
1. A semiconductor chip set with double-sided off-chip bonding structure, which is characterized in comprising a first off-chip bonding structure which is formed above a first surface of the semiconductor chip set, and a second off-chip bonding structure which is formed above a second surface of the semiconductor chip set, wherein each of the off-chip bonding structures above the first surface and second surface of the semiconductor chip set can be used for connecting to a signal or power connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump in the semiconductor chip set, and, when the first off-chip bonding structure and the second off-chip bonding structure are connected to a same substrate providing the signal or power connecting points, a first point formed on the same substrate and connected to the first off-chip bonding structure is different from a second point formed on the same substrate and connected to the second off-chip bonding structure.
2. The semiconductor chip set according to claim 1, wherein a chip circuitry is formed near the first surface and connected to the first off-chip bonding structure.
3. The semiconductor chip set according to claim 1, wherein a chip circuitry is formed near the first surface and connected to the second off-chip bonding structure through a through-silicon-via set penetrating the semiconductor chip set.
4. The semiconductor chip set according to claim 1, wherein the semiconductor chip set is a single semiconductor chip, the first surface and the second surface are opposite two surfaces of the single semiconductor chip, and a chip circuitry is formed near the first surface, connected to the first off-chip bonding structure and further connected to the second off-chip bonding structure through a through-silicon-via penetrating the single semiconductor chip.
5. The semiconductor chip set according to claim 1, further comprising a plurality of semiconductor chips stacked together, wherein the semiconductor chips comprise a first chip and a second chip, a plurality of third bonding structures are respectively formed above opposite two surfaces of the first chip and formed above opposite two surfaces of the second chip, and the third bonding structures are used for connecting with signal or power terminals external to the stacked semiconductor chips.
6. The semiconductor chip set according to claim 5, wherein a first control circuit and a first operation circuit electrically connected to the first control circuit are arranged in the first chip, a second control circuit and a second operation circuit electrically connected to the second control circuit are arranged in the second chip, and the second control circuit is electrically connected to the first operation circuit through a through-silicon-via penetrating the first chip;
- wherein the first operation circuit is controlled by the first control circuit when the first control circuit is turned on, and the first operation circuit and the second operation circuit are controlled by the second control circuit at the same time when the first control circuit is turned off.
7. The semiconductor chip set according to claim 1, further comprising a plurality of memory chips stacked together.
8. A semiconductor chip with double-sided off-chip bonding structure, which is characterized in that the semiconductor chip comprises a first surface and a second surface opposite to the first surface, the first surface is adapted to be disposed with a chip circuitry, at least one first off-chip bonding structure is formed above the first surface, at least one a second off-chip bonding structure is formed above the second surface, and, at least one of the at least one second off-chip bonding structure is connected to the chip circuitry through a through-silicon-via;
- wherein, at least one of the at least one first off-chip bonding structure is connected to a first power or a first signal external to the semiconductor chip, at least one of the at least one second off-chip bonding structure is connected to a second power or a second signal external to the semiconductor chip, and, when the at least one first off-chip bonding structure and the at least one second off-chip bonding structure are connected to a same substrate, a first point formed on the same substrate and connected to the at least one first off-chip bonding structure is different from a second point formed on the same substrate and connected to the at least one second off-chip bonding structure.
9. The semiconductor chip according to claim 8, wherein the at least one of the at least one first off-chip bonding structure is connected to the first power or the first signal through a first bonding wire or a first micro bump, and the at least one of the at least one second off-chip bonding structure is connected to the second power or the second signal through a second bonding wire or a second micro bump.
10. A semiconductor chip set, comprising a plurality of semiconductor chips, each of the semiconductor chips being as the semiconductor chip recited in claim 8, and the semiconductor chips are connected together through connecting a part or all of the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of one of the semiconductor chips to a part or all of the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of another one of the semiconductor chips;
- wherein, the at least one first off-chip bonding structure or the at least one second off-chip bonding structure of any one of the semiconductor chips is adapted to be connected to receive power external to the semiconductor chip set or is adapted to be connected to communicate signals with elements external to the semiconductor chip set.
20140175673 | June 26, 2014 | Kim |
Type: Grant
Filed: Jan 2, 2020
Date of Patent: Apr 13, 2021
Patent Publication Number: 20200211930
Inventor: Gyh-Bin Wang (Hsinchu County)
Primary Examiner: Errol V Fernandes
Application Number: 16/732,771
International Classification: H01L 23/48 (20060101); H01L 25/065 (20060101); H01L 23/00 (20060101);