Chip Mounted On Chip Patents (Class 257/777)
  • Patent number: 11824044
    Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Ye, Hong Wan Ng
  • Patent number: 11817409
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 14, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • Patent number: 11817445
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11817373
    Abstract: A semiconductor arrangement and method of forming the semiconductor arrangement are provided. The semiconductor arrangement includes a device having a first surface and a second surface opposite the first surface. A first through substrate via (TSV) structure extends between the first surface and the second surface in a first region of the device. A second TSV structure extends between the first surface and the second surface in a second region of the device. The first TSV structure has a first cross-sectional area. The second TSV structure has a second cross-sectional area greater than the first cross-sectional area.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Jen-Yuan Chang
  • Patent number: 11810868
    Abstract: A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: November 7, 2023
    Inventor: Byeonguk Jeon
  • Patent number: 11810896
    Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
  • Patent number: 11804464
    Abstract: A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 31, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Keiichi Niwa
  • Patent number: 11791241
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes forming a conductive feature in a first wafer, and forming a first bonding layer over the conductive feature. The method includes forming a second bonding layer over a second wafer, and bonding the first wafer and the second wafer by bonding the first bonding layer and the second bonding layer. The method also includes forming a second transistor in a front-side of the second wafer, and after forming the second transistor in the front-side of the second wafer, forming a first TSV through the second wafer, wherein the first TSV stops at the conductive feature.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 11791310
    Abstract: Packaging structure is provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 17, 2023
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 11791311
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 17, 2023
    Assignee: NAGASE & CO., LTD.
    Inventor: Yoichiro Kurita
  • Patent number: 11791333
    Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11776946
    Abstract: A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: October 3, 2023
    Inventors: Junho Cho, Ohchul Kwon, Seungjin Cheon, Tea-Geon Kim, Bubryong Lee, Junglae Jung
  • Patent number: 11776877
    Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sameer S. Vadhavkar, Xiao Li, Steven K. Groothuis, Jian Li, Jaspreet S. Gandhi, James M. Derderian, David R. Hembree
  • Patent number: 11776922
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 3, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hajime Arai
  • Patent number: 11764192
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: September 19, 2023
    Inventors: Jihwan Hwang, Taehun Kim, Jihwan Suh, Soyoun Lee, Hyuekjae Lee, Jiseok Hong
  • Patent number: 11764187
    Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 19, 2023
    Assignee: Intel Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Thomas Wagner, Andreas Wolter, Andreas Augustin, Sonja Koller, Thomas Ort, Reinhard Mahnkopf
  • Patent number: 11742344
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 11735523
    Abstract: Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 22, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 11735526
    Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: August 22, 2023
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Zhitao Cao, Kunzhong Hu, Jun Zhai
  • Patent number: 11728334
    Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11715691
    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: August 1, 2023
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind S. Bhagavat, Rahul Agarwal, Chia-Hao Cheng
  • Patent number: 11710702
    Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Hung Wen Liu
  • Patent number: 11710514
    Abstract: First signaling indicative of instructions to enter a self-refresh (SREF) mode can be received concurrently by a plurality of memory dies. Responsive to a memory die of the plurality of memory dies entering the SREF mode, self-refreshing of memory banks of the memory die can be delayed, at the memory die and based on fuse states of an array of fuses of the memory die, an amount of time relative to receipt of the signaling by the memory die. Delaying self-refreshing of memory banks of memory dies in a staggered, or asynchronous, manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christopher D. Wieduwilt, Lawrence D. Smith, James S. Rehmeyer
  • Patent number: 11705430
    Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyeong Kim, Young Lyong Kim, Geol Nam
  • Patent number: 11705437
    Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: July 18, 2023
    Assignee: ZHEJIANG LAB
    Inventors: Qingwen Deng, Kun Zhang, Shunbin Li, Ruyun Zhang
  • Patent number: 11699682
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 11, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11694996
    Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: July 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuekjae Lee, Un-Byoung Kang, Sang Cheon Park, Jinkyeong Seol, Sanghoon Lee
  • Patent number: 11694987
    Abstract: Semiconductor packages including active package substrates are described. In an example, the active package substrate includes an active die between a top substrate layer and a bottom substrate layer. The top substrate layer may include a via and the active die may include a die pad. An anisotropic conductive layer may be disposed between the via and the die pad to conduct electrical current unidirectionally between the via and the die pad. In an embodiment, the active die is a flash memory controller and a memory die is mounted on the top substrate layer and placed in electrical communication with the flash memory controller through the anisotropic conductive layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 11694966
    Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Lung Pan, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 11682643
    Abstract: A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventors: Ju Il Eom, Woo Jin Lee, Hyung Ho Cho
  • Patent number: 11669265
    Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Robert Walker
  • Patent number: 11664341
    Abstract: The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 30, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11658153
    Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chun-Hung Lin
  • Patent number: 11658152
    Abstract: A die bonding structure includes a first die and a second die. The first die includes a first sealing ring and a plurality of first metal contacts, wherein sidewalls of the first metal contacts align a sidewall of the first sealing ring. The second die includes a second sealing ring and a plurality of second metal contacts, wherein sidewalls of the second metal contacts align a sidewall of the second sealing ring. The first metal contacts are directly bonded to the second metal contacts, respectively, and the first sealing ring is directly bonded to the second sealing ring.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: May 23, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11658172
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 11652087
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: May 16, 2023
    Assignee: Tahoe Research, Ltd.
    Inventor: Aiping Tan
  • Patent number: 11626380
    Abstract: A semiconductor package includes a package substrate including a first substrate channel pad and a second substrate channel pad, a chip stack including a plurality of semiconductor chips stacked on the package substrate to be offset in a first direction, wherein first semiconductor chips located on odd layers from among the plurality of semiconductor chips and second semiconductor chips located on even layers from among the plurality of semiconductor chips are offset in a second direction perpendicular to the first direction, each of the first semiconductor chips includes a first chip channel pad, and each of the second semiconductor chips includes a second chip channel pad, first inter-chip connection wires configured to electrically connect the first chip channel pads of the first semiconductor chips to one another, second inter-chip connection wires configured to electrically connect the second chip channel pads of the second semiconductor chips to one another.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunjun Noh, Keunho Choi
  • Patent number: 11621208
    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11600597
    Abstract: The present disclosure provides a semiconductor package, including a substrate, a semiconductor die, and a conductive bump. The substrate has a first surface and a second surface opposite to the first surface. The substrate further includes a conductive line surrounded by a dielectric, and a conductive via connected to the conductive line and protruding from the dielectric at the second surface. The semiconductor die is connected to the first surface of the substrate. The conductive bump is connected to the conductive via at the second surface.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11594522
    Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
  • Patent number: 11570905
    Abstract: A method of manufacturing component carriers is disclosed. The method includes providing a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, forming a first hole in a core of the stack and subsequently embedding a first component in the first hole, thereafter forming a second hole in the same core of the stack and subsequently embedding a second component in the second hole. A component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A first hole is formed in a core of the stack. A first component is embedded in the first hole. A second hole is formed in the same core of the stack and subsequently a second component is embedded in the second hole.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: January 31, 2023
    Assignee: AT&S(Chongqing) Company Limited
    Inventor: Artan Baftiri
  • Patent number: 11552065
    Abstract: A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 10, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Bin Wan Mat Wan Azha
  • Patent number: 11545443
    Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 11545419
    Abstract: A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: January 3, 2023
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takuya Kadoguchi, Takahiro Hirano, Arata Harada, Tomomi Okumura, Keita Fukutani, Masayoshi Nishihata
  • Patent number: 11538789
    Abstract: According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: December 27, 2022
    Assignee: Kioxia Corporation
    Inventor: Yoshiyuki Kosaka
  • Patent number: 11532532
    Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is exposed; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a protection layer including a plurality of beads embedded within a top region of the polymeric gel.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 20, 2022
    Assignee: NXP USA, INC.
    Inventor: Michael B. Vincent
  • Patent number: 11532498
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 11521958
    Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang
  • Patent number: 11521923
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a layer of dielectric material; a conductive pad at least partially on a top surface of the layer of dielectric material; and a layer of material on side surfaces of the conductive pad, wherein the layer of material does not extend onto the top surface of the layer of dielectric material. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Kevin McCarthy
  • Patent number: 11515202
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: November 29, 2022
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong