Chip Mounted On Chip Patents (Class 257/777)
  • Patent number: 11031376
    Abstract: A chip package including a first semiconductor die, conductive pillars, a dielectric structure, a second semiconductor die and insulating encapsulant is provided. The first semiconductor die includes a top surface having a first region and a second region. The conductive pillars are disposed over the second region of the first semiconductor die. The dielectric structure includes a first support portion disposed on the first region of the semiconductor die, and a second support portion physically separated from the first semiconductor die. The second semiconductor die is stacked over the first support portion and the second support portion, and is electrically connected to the first semiconductor die through the conductive pillars. The insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin, Chun-Yen Lan, Kai-Ming Chiang
  • Patent number: 11024603
    Abstract: A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 1, 2021
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Chi-An Wang, Hsien-Wen Hsu
  • Patent number: 11018133
    Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11011486
    Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Yu Yang
  • Patent number: 10998282
    Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: David Unruh, Srinivas V. Pietambaram
  • Patent number: 10978432
    Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kilsoo Kim
  • Patent number: 10978399
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure. The die interconnect substrate comprises a via portion formed on the first bridge die pad of the bridge die. An average angle between a surface of the first bridge die pad and a sidewall of the via portion lies between 85° and 95°.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Sai Boyapati, Wei-Lun Kane Jen, Javier Soto Gonzalez
  • Patent number: 10978377
    Abstract: A semiconductor chip set with double-sided off-chip bonding structure in the disclosure comprises at least one first off-chip bonding structure formed above a first surface of the semiconductor chip set, and at least one second off-chip bonding structure formed above a second surface of the semiconductor chip set, wherein the first surface is opposite to the second surface and each of the first off-chip bonding structure and the second off-chip bonding structure is used for connecting to an electrical connecting point external to the semiconductor chip set through bonding wire, through-silicon via (TSV) or micro bump.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: April 13, 2021
    Inventor: Gyh-Bin Wang
  • Patent number: 10978374
    Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunki Kim, Sangsoo Kim, Seung Hwan Kim, Kyung Suk Oh, Yongkwan Lee, Jongho Lee
  • Patent number: 10978426
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax
  • Patent number: 10978413
    Abstract: A circuit system having compact decoupling structure, including: a mother board; at least one circuit unit, each having a substrate, a logic-circuit die, a plurality of first metal contacts, and a plurality of second metal contacts, the substrate having a first surface and a second surface, the first metal contacts being formed on the first surface and soldered onto the mother board, the second metal contacts being formed on the logic-circuit die and soldered onto the second surface to form flip-chip pillars, and the flip-chip pillars determining a height of a gap between the die and the substrate; and at least one decoupling unit for providing an AC signals decoupling function for the at least one circuit unit; wherein each of the at least one decoupling unit is placed in the gap of one said circuit unit and includes a mother die and at least one stack-type integrated-passive-device die.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 13, 2021
    Assignee: AP MEMORY TECHNOLOGY CORP.
    Inventors: Masaru Haraguchi, Yoshitaka Fujiishi
  • Patent number: 10971437
    Abstract: A chip package structure can include: a lead frame having a plurality of pins, a first die pad, and a second die pad; a first die and a second die, where a first surface of the first die is installed on the first die pad, and a first surface of the second die is installed on the second die pad; a plurality of pads installed on a second surface of the first die and a second surface of the second die; and bonding wires including a first set of bonding wires with each having one terminal connected to pads of the first die, and a second set of bonding wires with each having one terminal connected to pads of the second die for connectivity between the first die and the second die, and between the plurality of pins and the first die and the second die.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 6, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Shijie Chen
  • Patent number: 10964659
    Abstract: A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Patent number: 10964668
    Abstract: Transistor packages in space-constrained applications are disclosed. An apparatus may comprise a first transistor package and a second transistor package, wherein the first transistor package is stacked upon the second transistor package. The apparatus may further comprise a cover coupled to a printed circuit board (PCB) that is configured to cover at least a portion of the stacked first and second transistor packages. The first and second transistor package may be components in a power circuit that is configured to down-convert a received voltage from a first voltage level to a second, lower voltage level.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 30, 2021
    Assignee: PGS GEOPHYSICAL AS
    Inventor: Jose Miguel Salgado Escuadra
  • Patent number: 10957662
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 23, 2021
    Inventor: Chengwei Wu
  • Patent number: 10950511
    Abstract: Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 16, 2021
    Assignee: Medtronic, Inc.
    Inventors: Mark R. Boone, Mark E. Henschel
  • Patent number: 10950512
    Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Woong Yu, So Hyun Jung
  • Patent number: 10943881
    Abstract: A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-nee Jang, KyungSeon Hwang, SunWon Kang
  • Patent number: 10930622
    Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
  • Patent number: 10916489
    Abstract: Disclosed herein is an apparatus that includes a memory cell army, a plurality of TSVs penetrating a semiconductor chip, an output circuit configured to output a data to the TSVs, an input circuit configured to receive a data from the TSVs, a pad supplied with a data from outside, and a control circuit configured to write the data to the memory cell array, read the data from the memory cell array, and transfer the data from the memory cell array to the input circuit via the output circuit and the TSVs.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Naohisa Nishioka, Seiji Narui
  • Patent number: 10916507
    Abstract: A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L Arvin, Brian W Quinlan, Steve Ostrander, Thomas Weiss, Mark W Kapfhammer, Shidong Li
  • Patent number: 10910364
    Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: February 2, 2021
    Assignee: MONOLITAIC 3D INC.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 10903156
    Abstract: An electronic device is disclosed. In an embodiment an electronic device includes a carrier board having an upper surface and an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a top side facing away from the upper surface of the carrier board, and sidewalls connecting the mounting side to the top side, wherein the electronic chip has equal to or less than 5 stud bumps per square millimeter of a base area of the mounting side, and wherein a laminated polymer hood at least partly covers the top side of the electronic chip and extends onto the upper surface of the carrier board.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 26, 2021
    Assignee: TDK CORPORATION
    Inventor: Wolfgang Pahl
  • Patent number: 10895512
    Abstract: A pressure measuring arrangement is proposed. The pressure measuring arrangement includes a first MEMS pressure sensor arranged on a carrier, and also a second MEMS pressure sensor arranged on the carrier. Furthermore, the pressure measuring arrangement includes an integrated circuit arranged on the carrier, the integrated circuit being coupled to the first MEMS pressure sensor and the second MEMS pressure sensor.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 19, 2021
    Inventor: Dirk Hammerschmidt
  • Patent number: 10886149
    Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor device is disposed on the substrate. The semiconductor device includes a first lateral surface. The underfill is disposed between the substrate and the semiconductor device. The underfill includes a first lateral surface. The first lateral surface of the underfill and the first lateral surface of the semiconductor device are substantially coplanar.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10879293
    Abstract: There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takahisa Furuhashi
  • Patent number: 10867943
    Abstract: Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou, Tung-Hsien Wu
  • Patent number: 10867890
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Sung-Yueh Wu
  • Patent number: 10861832
    Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 10861763
    Abstract: An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
  • Patent number: 10854392
    Abstract: A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in a first direction, a first main surface including a first flat region facing in the first direction, and a second main surface including a second flat region facing in the first direction; and a pair of external electrodes connected to the internal electrodes and facing each other in a second direction orthogonal to the first direction, a dimension of the ceramic body in the first direction being 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a third direction orthogonal to the first and second directions, the first flat region being formed at a center portion of the first main surface in the second direction, the second flat region being formed at a center portion of the second main surface in the third direction.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Hiroaki Sato
  • Patent number: 10847443
    Abstract: Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10833475
    Abstract: An optoelectronic lighting device includes an optoelectronic semiconductor chip including a top side and an underside opposite the top side, wherein a semiconductor layer sequence is formed between the top side and the underside, the semiconductor layer sequence includes an active zone that generates electromagnetic radiation, and a barrier for a bonding material flowing on account of cohesive bonding of the semiconductor chip to a carrier is formed at one of the top side and the underside.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: November 10, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Christoph Eichler, Sven Gerhard
  • Patent number: 10825792
    Abstract: Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10826483
    Abstract: A power chip and a bridge circuit are disclosed in the present disclosure. The power chip includes a metal region and a wafer region, wherein the power chip further includes: a first power switch, formed in the wafer region; and a second power switch, formed in the wafer region, wherein the first and second power switches constitute an upper bridge arm and a lower bridge arm of a bridge circuit, respectively. At least one of the upper bridge arm and the lower bridge arm includes two or more power switches which are connected in parallel with each other, and the first and second power switches are arranged alternatively along at least one dimension direction.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: November 3, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Yan Chen, Xiaoni Xin, Le Liang, Shouyu Hong, Jianhong Zeng
  • Patent number: 10820409
    Abstract: According to a first aspect, there is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 27, 2020
    Assignee: GRAPHCORE LIMITED
    Inventor: Stephen Felix
  • Patent number: 10811334
    Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Archana Venugopal, Luigi Colombo, Robert Reid Doering
  • Patent number: 10811394
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Patent number: 10811395
    Abstract: A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 20, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10811392
    Abstract: A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Toshiki Hirano, Vipin Ayanoor-Vitikkate, Nagesh Vodrahalli
  • Patent number: 10811388
    Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Patent number: 10804189
    Abstract: A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 13, 2020
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventor: Hsin-Chang Tsai
  • Patent number: 10804243
    Abstract: Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: James D. Kelly, William H. Radke, Steven J. Sfarzo
  • Patent number: 10804212
    Abstract: A semiconductor package includes a package substrate, a first semiconductor device on an upper surface of the package substrate, a second semiconductor device on an upper surface of the first semiconductor device, a first connection bump attached to a lower surface of the package substrate, a second connection bump interposed between and electrically connected to the package substrate and the first semiconductor device, and a third connection bump interposed between and electrically connected to the first semiconductor device and the second semiconductor device. The first semiconductor device has an edge and a step at the edge.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Kwon Ko, Jun-Yeong Heo, Un-Byoung Kang, Ja-Yeon Lee
  • Patent number: 10804139
    Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 13, 2020
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Patent number: 10790270
    Abstract: Provided is a stacked semiconductor package, which has various kinds of semiconductor chips with various sizes and is capable of miniaturization. The stacked semiconductor package includes a base substrate layer and a sub semiconductor package disposed on a top surface of the base substrate layer. The sub semiconductor package includes a plurality of sub semiconductor chips spaced apart from one another, and a sub mold layer filling spaces between the plurality of sub semiconductor chips to surround side surfaces of the plurality of sub semiconductor chips. The stacked semiconductor package includes at least one main semiconductor chip stacked on the sub semiconductor package, the at least one main semiconductor chip being electrically connected to the base substrate layer through first electrical connection members.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong-ha Lee
  • Patent number: 10790172
    Abstract: The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: September 29, 2020
    Assignee: JABIL INC.
    Inventors: Lim Lai Ming, Zambri Bin Samsudin
  • Patent number: 10777502
    Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Wei-Ting Chen
  • Patent number: 10777527
    Abstract: A method for transferring a micro device is provided. The method includes: preparing a transfer plate with the micro device thereon in which the micro device is in contact with a picked-up surface of the transfer plate; forming a structure including the micro device, a contact pad of a receiving substrate, and some water therebetween in which two opposite surfaces of the water are respectively in contact with the micro device and a bound surface of the contact pad, and a hydrophilicity of the bound surface of the contact pad facing the transfer plate is greater than a hydrophilicity of the picked-up surface of the transfer plate facing the receiving substrate; and evaporating the water such that the micro device is bound to and in contact with the contact pad.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 15, 2020
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventor: Li-Yi Chen
  • Patent number: 10777539
    Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shin Chu, Kuan-Chieh Huang, Pao-Tung Chen, Shuang-Ji Tsai, Yi-Hao Chen, Feng-Kuei Chang