Chip Mounted On Chip Patents (Class 257/777)
  • Patent number: 11450614
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Patent number: 11417538
    Abstract: A semiconductor package includes a die pad, a die, a first lead, a plurality of second leads, and a mold material. The die is electrically coupled to the die pad. The first lead is electrically coupled to the die. The plurality of second leads are electrically coupled to the die. The plurality of second leads are adjacent to the first lead. The mold material encapsulates at least a portion of the die pad, the die, the first lead, and the plurality of second leads. Each of the plurality of second leads extends a farther distance from the mold material than the first lead.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thai Kee Gan, Edmund Sales Cabatbat
  • Patent number: 11410973
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Patent number: 11410953
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 11404355
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 11404395
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 2, 2022
    Inventors: Jihwan Hwang, Taehun Kim, Jihwan Suh, Soyoun Lee, Hyuekjae Lee, Jiseok Hong
  • Patent number: 11397687
    Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: July 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 11393794
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, at least one surface mount component operably coupled to conductive traces of at least one dielectric material, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Randon K. Richards, Owen R. Fay, Aparna U. Limaye, Dong Soon Lim
  • Patent number: 11393783
    Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Po-Hao Tsai, Jing-Cheng Lin
  • Patent number: 11393764
    Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geol Nam, Gunho Chang
  • Patent number: 11380595
    Abstract: A semiconductor wafer includes a first chip region and a second chip region spaced apart from each other by a scribe lane region. The semiconductor wafer also includes a test pad disposed in the scribe lane region. The semiconductor wafer additionally includes a protective layer partially covering the first chip region, the second chip region, and the scribe lane region, wherein the protective layer covers a portion of the test pad adjacent to the first chip region and leaves a remaining portion of the first test pad exposed.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyun Chul Seo
  • Patent number: 11373977
    Abstract: A system-in-package (SiP) incorporating] is disclosed. In embodiments, the host die defines a substantially horizontal plane (e.g., via its active side). One or more vertical dielets are attached to, and interconnected with, the active side of the host die in a substantially vertical configuration (e.g., perpendicular to the host die). Due to the perpendicular orientation of the dielets, the SiP incorporates thermal spreaders in thermal contact with the active side of the host die as well as the inactive sides of the dielets, allowing for thermal dissipation from the host dies and dielets without the need for through silicon vias.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 28, 2022
    Assignee: Rockwell Collins, Inc.
    Inventor: Reginald D. Bean
  • Patent number: 11373979
    Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mung Suan Heng, Kok Chua Tan, Vince Chan Seng Leong, Mark S. Johnson
  • Patent number: 11367708
    Abstract: Embodiments of the invention include a microelectronic device that includes a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. An interposer substrate can provide a spacing between the first and second substrates.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Georgios C. Dogiamis, Telesphor Kamgaing
  • Patent number: 11362485
    Abstract: Embodiments of the present disclosure include method for sequentially mounting multiple semiconductor devices onto a substrate having a composite metal structure on both the semiconductor devices and the substrate for improved process tolerance and reduced device distances without thermal interference. The mounting process causes “selective” intermixing between the metal layers on the devices and the substrate and increases the melting point of the resulting alloy materials.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: June 14, 2022
    Assignee: Aeva, Inc.
    Inventors: Zhizhong Tang, Pradeep Srinivasan, Kevin Masuda, Wenjing Liang
  • Patent number: 11362063
    Abstract: A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 14, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, John T. Contreras
  • Patent number: 11355452
    Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: June 7, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dong Won Son, Byeonghoon Kim, Sung Ho Choi, Sung Jae Lim, Jong Ho Shin, SungWon Cho, ChangOh Kim, KyoungHee Park
  • Patent number: 11348863
    Abstract: In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 31, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Patent number: 11342246
    Abstract: An integrated circuit (IC) package is described. The IC package includes a die. The die including an active layer on a substrate and through substrate vias (TSVs) coupled to the active layer and extending through the substrate to a backside surface of the die. The IC package also includes integrated passive devices (IPDs) on the backside surface of the die and coupled to the active layer through the TSVs. The IC package further includes back-end-of-line (BEOL) layers on the active layer. The IC package also includes a metallization structure on the BEOL layers. The IC package also includes an under bump metallization layer on the metallization structure. The IC package further includes package bumps on the first under bump metallization layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 24, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Jonghae Kim, Hong Bok We
  • Patent number: 11342315
    Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventors: Juil Eom, Bok Kyu Choi, Jae Hoon Lee, Jin Woo Park
  • Patent number: 11342320
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
  • Patent number: 11329027
    Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventor: Bilal Khalaf
  • Patent number: 11322445
    Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Yidnekachew S. Mekonnen, Dae-Woo Kim, Kemal Aygun, Sujit Sharan
  • Patent number: 11315902
    Abstract: Multi-semiconductor chip modules that have a substrate with a substrate surface, one or more first substrate connections, and one or more second substrate connections. One or more first semiconductor chips (chips) has one or more larger first chip connections and one or more smaller first chip connections on a first chip bottom surface. One or more of the larger first chip connections physically and electrically connected to a respective first substrate connection. One or more second chips has one or more larger second chip connections and one or more smaller second chip connections on a second chip bottom surface. One or more of the larger second chip connections physically and electrically connected to a respective second substrate connection. A bridge has a bridge thickness, a bridge surface, and one or more bridge connections on the bridge surface. A first part of the bridge surface is under the first chip bottom surface and a second part of the bridge surface is under the second chip bottom surface.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventor: John Knickerbocker
  • Patent number: 11315893
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11315003
    Abstract: A transaction card (smartcard) having a front “continuous” (with no slit) metal layer (ML, CML) with an opening (MO) for a dual-interface transponder chip module (TCM) having a module antenna (MA) on its bond side. A magnetic shielding layer (MSL) comprising ferrite material disposed below the front face continuous metal layer. An amplifying element, booster antenna circuit (BAC) disposed under the magnetic shielding layer. A rear discontinuous metal layer (ML, DML) with a slit (S) and a metal ledge surrounding the module opening to function as a coupling frame (CF). A rear plastic layer formed of non-RF impeding material may support a magnetic stripe and security elements (signature panel and hologram). A portion of the front face continuous metal layer may protrude downward into the magnetic shielding layer and booster antenna circuit layer. The rear discontinuous metal layer may have an additional slit to regulate the activation distance.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 26, 2022
    Assignee: Federal Card Services, LLC
    Inventor: David Finn
  • Patent number: 11309282
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes steps of providing semiconductor wafer having a plurality of device chips disposed thereon, wherein each of the plurality of device chips has an active area and an inactive area arranged around the active area; forming a plurality of the openings, wherein each of the plurality of openings is formed in a back surface of the semiconductor wafer and forms an opening into the inactive area; and disposing a protecting material within the openings and over the back surface of the semiconductor wafer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11302706
    Abstract: Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a unified semiconductor chip includes a first semiconductor structure including one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The unified semiconductor chip also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The unified semiconductor chip further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 12, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Weihua Cheng
  • Patent number: 11302611
    Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Paul Merle Emerson, Sandeep Shylaja Krishnan
  • Patent number: 11296062
    Abstract: A package includes a building block. The building block includes a device die, an interposer bonded with the device die, and a first encapsulant encapsulating the device die therein. The package further includes a second encapsulant encapsulating the building block therein, and an interconnect structure over the second encapsulant. The interconnect structure has redistribution lines electrically coupling to the device die. A power module is over the interconnect structure. The power module is electrically coupled to the building block through the interconnect structure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tin-Hao Kuo
  • Patent number: 11296065
    Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Techi Wong, Po-Yao Chuang, Shuo-Mao Chen, Meng-Wei Chou
  • Patent number: 11289440
    Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Bret K. Street
  • Patent number: 11289452
    Abstract: A method of manufacturing a component carrier includes a step of stacking and connecting a first component and a second component to one another to form a cluster and thereafter, a step of inserting the cluster into a cavity of a base structure. A component carrier has a base structure with a cavity; a cluster having a first component stacked and connected with a second component, wherein the cluster is arranged in the cavity. A height difference between opposing lateral sidewalls of the cluster is less than 15 ?m.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: March 29, 2022
    Assignee: AT&S (Chongqing) Company Limited
    Inventor: Jeesoo Mok
  • Patent number: 11282818
    Abstract: A semiconductor device in an embodiment includes a first chip on a substrate and a second chip adhered to a first region of the first chip using a first adhesive layer. The second chip is positioned so a second region of the first semiconductor is not overlapped. The first adhesive layer covers a lower surface of the second chip but not the second region. A third chip is adhered to a third region of the second chip with a second adhesive layer. The third chip is positioned so a fourth region of the second chip is not overlapped. The second adhesive layer covers a lower surface of the third chip but not the fourth region. An end of the second adhesive layer is above the second region, but not contacting. A coating covers the fourth region and the ends of the second adhesive layer and third chip.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Toshimitsu Arai
  • Patent number: 11276635
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Sujit Sharan, Kemal Aygun, Zhiguo Qian, Yidnekachew Mekonnen, Zhichao Zhang, Jianyong Xie
  • Patent number: 11276650
    Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 15, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: YongIk Choi, Chris Chung, Michael Leary, Domingo Figueredo, Chang Kyu Choi, Sarah Haney, Li Sun
  • Patent number: 11264069
    Abstract: An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Johnson, Jung-Hwa Choi
  • Patent number: 11264350
    Abstract: A semiconductor device includes an interconnect structure disposed over a first semiconductor die. The first semiconductor die includes a semiconductor substrate and a first conductive pad disposed over the semiconductor substrate, and the first conductive pad is covered by the interconnect structure. The semiconductor device also includes dielectric spacers surrounding the interconnect structure. An interface between the dielectric spacers and the interconnect structure is curved. The semiconductor device further includes a dielectric layer surrounding the dielectric spacers, and a second semiconductor die bonded to the dielectric layer and the interconnect structure. The second semiconductor die includes a second conductive pad, and the interconnect structure is covered by the second conductive pad.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11264357
    Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: March 1, 2022
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 11264366
    Abstract: Provided is a module which has a package-on-package structure including a redistribution layer and can be easily reduced in height. A module includes an upper module including a substrate, a first component, and a sealing resin layer, and a lower module including an intermediate layer and a redistribution layer. The first component is connected to the redistribution layer with a columnar conductor interposed therebetween and provided in the intermediate layer, and both the first component and a second component are rewired by the redistribution layer. By fixing a resin block containing the second component to a lower surface of the substrate by a fixing conductor, positional deviation of the second component can be prevented. Further, by polishing an upper surface of the resin block, it is possible to improve the flatness.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yukio Yamamoto
  • Patent number: 11257792
    Abstract: A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 11251144
    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
  • Patent number: 11250904
    Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: Piecemakers Technology, Inc.
    Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
  • Patent number: 11239032
    Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Yeol Lee, Ji Hong Jo, Yoo Jeong Lee, Myung Jun Park, Jong Ho Lee, Hye Young Choi, Jae Hyun Lee, Hyun Hee Gu
  • Patent number: 11239177
    Abstract: A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Sukwon Lee, Bok Gyu Min
  • Patent number: 11239203
    Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 1, 2022
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Steven P. Young
  • Patent number: 11239103
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 11230767
    Abstract: A substrate W having a non-plateable material portion 31 and a plateable material portion 32 formed on a surface thereof is prepared, and then, a catalyst is selectively imparted to the plateable material portion 32 by performing a catalyst imparting processing on the substrate W. Thereafter, a plating layer 35 is selectively formed on the plateable material portion 32 by supplying a plating liquid M1 onto the substrate W. The plating liquid M1 contains an inhibitor which suppresses the plating layer 35 from being precipitated on the non-plateable material portion 31.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 25, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuichiro Inatomi, Takashi Tanaka, Kazutoshi Iwai
  • Patent number: 11230617
    Abstract: A resin composition contains a 2-methylene-1,3-dicarbonyl compound and an initiator. The 2-methylene-1,3-dicarbonyl compound has a molecular weight of 180 to 10,000, and the initiator contains a basic substance having a pKa of 8 or greater.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 25, 2022
    Assignee: NAMICS CORPORATION
    Inventors: Fuminori Arai, Kazuki Iwaya
  • Patent number: 11233030
    Abstract: An electrical device with printed interconnects between packaged integrated circuit components and a substrate as well as a method for printing interconnects between packaged integrated circuit components and a substrate are disclosed. An electrical device with printed interconnects may include a dielectric layer forming a continuous surface between a substrate and a terminal face of an integrated circuit component. The electrical device may further include interconnects formed from a layer of material printed across the continuous surface formed by the dielectric layer to connect electrical terminals on the substrate to electrical terminals on the terminal face of the integrated circuit component.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 25, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Brandon C. Hamilton, Kyle B. Snyder, Alan P. Boone