Slope compensation method for DC-DC converter

A voltage regulator circuit comprises a switching circuit, a dynamic clamp circuit, and a comparison circuit. The switching circuit adjusts a switching duty cycle to produce a regulated output voltage using an error signal representative of a difference between a target voltage value and the output voltage. The dynamic clamp circuit determines a maximum peak inductor current command value using the output voltage and an input voltage of the voltage regulator circuit. The comparison circuit sets a maximum peak inductor current value using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage. The comparison circuit compares a sensed inductor current to a peak inductor current value and enables switching of the voltage regulator system according to the comparison.

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Description
FIELD OF THE DISCLOSURE

This document relates to converter circuits and in particular to slope compensation in direct current to direct current (DC to DC) converter circuits.

BACKGROUND

Converter circuits can be used to generate a regulated output from a circuit input. For example, a buck voltage converter circuit uses an input voltage to generate a regulated output voltage less than the input voltage, and boost converter circuit generates a regulated output voltage greater than the input voltage. One option for regulation of a converter circuit is current-mode control. In current-mode control, switching of energy to an inductor of the converter circuit is controlled by monitoring the inductor current.

SUMMARY OF THE DISCLOSURE

This document relates generally to electronic circuits for current and voltage regulation and more specifically to improvements in current-mode control of voltage converter circuits. In some aspects, a voltage regulator circuit includes a switching circuit, a dynamic clamp circuit, and a comparison circuit. The switching circuit adjusts a switching duty cycle to produce a regulated output voltage using an error signal representative of a difference between a target voltage value and the output voltage. The dynamic clamp circuit determines a maximum peak inductor current command value using the output voltage and an input voltage of the voltage regulator circuit. The comparison circuit sets a maximum peak inductor current value using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage; compares a sensed inductor current to a peak inductor current value; and enables switching of the voltage regulator system according to the comparison.

In some aspects, a method of operating a voltage converter circuit includes receiving energy at the voltage regulator circuit and generating an output voltage according to a switching cycle; determining a maximum peak inductor current command value using the output voltage and an input voltage of the voltage regulator circuit; setting a maximum peak inductor current value of the voltage regulator circuit using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage; comparing a sensed inductor current to a peak inductor current value, and enabling switching of the voltage regulator circuit according to the comparison.

In some aspects, a voltage regulator circuit includes a switching circuit, a dynamic clamp circuit, and a comparison circuit. The switching circuit adjusts a switching duty cycle to produce a regulated output voltage greater than an input voltage using an error signal representative of a difference between a target voltage value and the output voltage. The dynamic clamp circuit determines a multiplier using an output current and a difference between the input voltage and an output voltage; and modifies a base clamp voltage value using the multiplier to set a maximum peak inductor current command value. The comparison circuit sets a maximum peak inductor current value using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage; compares a sensed inductor current to a peak inductor current value; and enables switching of the voltage regulator circuit according to the comparison.

This section is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

FIG. 1 is a schematic of an example of a voltage regulator circuit.

FIG. 2 is an illustration of a waveform of inductor current

FIGS. 3A and 3B are illustrations of waveforms of inductor current and slope compensation current.

FIG. 4 is a further illustration of waveforms of inductor current and slope compensation current.

FIG. 5 is a flow diagram of a method of operating a voltage regulator circuit.

FIG. 6 is a schematic of another example of a voltage regulator circuit.

FIG. 7A is a block diagram of portions of an example of a dynamic clamp circuit.

FIG. 7B is a block diagram of portions of an example of a voltage clamp circuit.

FIG. 8 is a circuit diagram of an example of a clock circuit and a slope current circuit.

FIG. 9 is an illustration of waveforms of the signals in FIG. 8.

FIG. 10 is a schematic of another example of a voltage regulator circuit.

FIG. 11 is a block diagram of portions of another example of a voltage clamp circuit.

FIG. 12 is a circuit diagram of another example of a clock circuit and a slope current circuit.

 DETAILED DESCRIPTION

FIG. 1 is a schematic of an example of a voltage regulator circuit 100. The circuit includes a top-gate transistor (TG), a bottom-gate transistor (BG), and an inductor 102. The circuit can include an output capacitor 104 electrically coupled to an output port and can supply an output voltage VOUT to an output load. The inductor 102 can be coupled between the output capacitor 104 and a circuit node 108. The bottom-gate transistor BG can be electrically coupled between the circuit node 108 and circuit ground, and the top-gate transistor TG can be electrically coupled between the circuit node 108 and an input port that is electrically coupled to an input voltage VIN.

The voltage regulator circuit 100 includes a switching circuit 110 or gate driver. The switching circuit 110 receives a clock signal from an oscillator 114 and the switching circuit 110 is configured (e.g., by logic circuitry) to use the clock signal to provide a switching duty cycle that includes a charge portion and a discharge portion. The voltage regulator circuit 100 receives electrical energy during the charge portion of the switching duty cycle.

During the charge portions of successive cycles, TG is turned on or active to raise the voltage of the circuit node 108 almost to the input voltage VIN. This initial activation drives a current through the inductor 102 and to the output capacitor 104 and load. During the discharge portion of the switching duty cycles, BG is turned on to pull the circuit node 108 almost to circuit ground. This second activation provides a gradually declining current from the energy stored in the inductor 102 to the output capacitor 104 and load.

The duration of the charge portion of the switching duty cycle can be automatically adjusted to maintain the output voltage VOUT at a specified level. The adjustment can be accomplished using a circuit feedback loop that includes an error amplifier circuit 112. The error amplifier circuit 112 generates an error signal (VCOMP) representative of a difference between a target voltage value and the voltage VOUT at the output of the voltage regulator circuit 100. The feedback loop can include a resistive divider 116 to provide a scaled representation of the output voltage to the error amplifier circuit 112 instead of the actual output voltage as a feedback voltage. The error amplifier circuit 112 compares the feedback voltage (VFB) with a voltage reference (VREF) to generate the error signal. The voltage regulator circuit may also include a filter circuit 118 to filter the output of the error amplifier.

The current through the inductor 102 can be sensed (e.g., by a sensing amplifier) and used to generate a sensed current signal (ISNS) representative of the inductor current. For current mode control, the output of the error amplifier circuit 112 can be converted to a current output, and the sensed inductor current can be compared to current signal using comparator circuit 126.

The comparator circuit 126 generates a PWM signal provided to the switching circuit 110. The PWM signal can be a digital signal that indicates when the error signal is less than or equal to the reference waveform signal. Alternatively, the digital signal may indicate when the error signal is greater than the reference waveform signal. The switching circuit 110 can include logic circuits to implement PWM switching control. The switching circuit 110 uses the period of the clock signal from the oscillator 114 and the PWM signal from the comparator circuit 126 to set the durations of the charge portion and discharge portion of the switching duty cycle according to the feedback loop. For example, the switching circuit 110 may turn on the top-gate transistor TG for a duration based on the comparison of the error signal and the reference waveform signal and then activate the bottom gate transistor BG for the remainder of each period of the clock signal.

Activation of the TG transistor generates a gradually increasing current in the inductor and activation of the BG transistor generates a gradually decreasing current in the inductor during each switching duty cycle. The increasing and then decreasing current maintains the feedback voltage at a value substantially equal to the reference voltage VREF. This activation sequence maintains the output voltage VOUT at the output port at the desired level regardless of the current demand at the load.

In the example shown in FIG. 1, the circuit topology and the target voltage value generate a regulated voltage for VOUT that is less than the voltage at the input VIN of the voltage regulator circuit (e.g., a buck converter circuit). Other examples can include, among other things, voltage regulator circuit topologies to generate a regulated VOUT that is greater than VIN (e.g., a boost converter circuit), circuit topologies to generate a regulated VOUT that can be either greater or less than VIN (e.g., a boost/boost converter circuit), and circuit topologies to generate an inverted value of VIN as the output voltage VOUT.

An issue with current-mode control is an instability referred to as sub-harmonic oscillation. FIG. 2 is an illustration of a waveform of inductor current IL. The inductor current IL rises during the charging portion (D) of the switching duty cycle (Ts) to a peak and decreases during the discharging portion of the switching duty cycle (Ts*(1-D)). The sub-harmonic oscillation instability is related to perturbations in the inductor current. Perturbations in inductor current may be caused by, among other things, jitter in the switching of comparator circuit 126 in FIG. 1 A perturbation in the inductor current at the beginning of a switching cycle can cause a shift in the inductor current at the end of the switching cycle. This shifting can lead to poor regulation of the output. If the duration of the charging portion of the switching cycle D is less than one half the switching cycle it can be shown that the shift in inductor current at the end of the switching cycle will decrease and die out after a number of switching cycles but will increase if D is more than one half.

Slope compensation can be used to eliminate sub-harmonic oscillation. Slope compensation uses an inductor current limit that decreases during a switching cycle. FIG. 3A is an illustration of a waveform of inductor current IL and a decreasing current limit (ICON-ISLP). In the example, ICON is an absolute maximum clamping current and ISLP is an increasing slope compensation current. The current limit (ICON-ISLP) begins a ICON at TS=0 and decreases with a slope. Energy is received into the voltage regulator and the inductor current IL increases during the charging portion of the switching cycle TS (ton=TON1) until it matches (ICON-ISLP), at which point the discharge portion of the switching cycle begins. The point at which IL matches (ICON-ISLP) is the peak inductor current IL,PK.

FIG. 3B is an illustration of a waveform of inductor current IL and decreasing current limit (ICON-ISLP), but with a different value of output voltage VOUT and a longer charging time (ton=TON2). The charging time may be increased due to an increase in VOUT. The inductor current IL rises more slowly with a lower slope than in FIG. 3A. The value of decreasing current limit (ICON-ISLP) that limits the inductor current is lower than in FIG. 3A. It can be seen from the examples of FIGS. 3A and 3B that a limitation of current control is that the maximum level of peak inductor current IL,PK,MAX is reduced as the switching duty cycle D increases. It is to be noted that the absolute maximum clamping current (ICON) is fixed to the same level of current in both FIG. 3A and FIG. 3B.

An improvement to slope compensation would be to have the maximum level of peak inductor current remain the same as the regulated output voltage level is changed. This would allow a voltage converter circuit to have the same drive capability with different values of output voltage. An approach to accomplish a constant or flat maximum level of peak inductor current IL for changing VOUT is to use a dynamic maximum clamping current (dynamic ICON) rather than a fixed maximum clamping current (fixed ICON).

FIG. 4 shows an illustration similar to FIG. 3A of a waveform of inductor current IL and a slope compensation current ISLP. The inductor current IL increases during the charging portion of a switching cycle TS (ton=TON1) until it matches (ICONMAX1-ISLP), and the discharge portion of the switching cycle then begins. The limit (ICONMAX1-ISLP) begins at a maximum inductor current command level (ICONMAX1) at TS=0 and decreases until the inductor current IL matches (ICONMAX1-ISLP), at which point the slope compensation is reset to the initial current level ICONMAX1. In steady state, the inductor current will match (ICONMAX1-ISLP) at the same current level (IL,PK,MAX) for each of the switching cycles.

FIG. 4 also shows an illustrator of a waveform of inductor current IL and a decreasing current limit, but with a different value of VOUT and a longer charging time (ton=TON2). The difference between the compensation in FIG. 4 from FIG. 3B is that the maximum peak inductor current command level (ICONMAX2) changes with the change in VOUT. In the example in FIG. 4, ICONMAX1 is greater than ICONMAX1. The slope of (ICONMAX2-ISLP) in FIG. 3B is the same as the slope of (ICONMAX1-ISLP) in FIG. 3A. Because the maximum peak inductor current command level is increased to the ICONMAX2 level, the current limit starts from a higher current level and the peak inductor current IL increases to a higher current level than in FIG. 3B before it matches (ICONMAX2-ISLP). With the corrected value of ICONMAX2 and a dynamic slope for ISLP, the maximum peak inductor current level (IL,PK,MAX) will be the same for both values of VOUT. Tying the maximum peak inductor current command level (ICONMAX) to the output voltage can result in the same maximum peak inductor current for different values of VOUT, i.e., the maximum peak inductor current level IL,PK,MAX will be flat for all values of the range of VOUT.

It should be noted that maximum peak inductor current level IL,PK,MAX is different from the peak inductor current level IL,PK. The peak inductor current level IL,PK is determined by the load and the output voltage at the load that the voltage converter will regulate. Only under certain conditions, such as the load at the output requiring a very high peak inductor current, does the peak inductor current level IL,PK reach the level of the maximum peak inductor current level IL,PK,MAX. The advantage of the approach in FIG. 4 is that the maximum peak inductor current available remains the same and doesn't decrease as the load at the output changes or the output voltage changes.

FIG. 5 is a flow diagram of a method 500 of operating a voltage regulator circuit. At 505, the voltage regulator circuit receives energy at the voltage regulator system and generates an output voltage according to a switching cycle. The inductor current IL of the voltage regulator circuit increases during a charging portion of the switching cycle and decreases during a discharge portion of the switching cycle.

At 510, a maximum peak inductor current command value ICONMAX is determined using the input to the voltage regulator circuit and the output voltage generated by the voltage regulator circuit. Because ICONMAX varies with the output voltage, the determined value of ICONMAX is not a fixed value.

At 515, a maximum peak inductor current value (IL,PK,MAX) of the voltage regulator circuit is set using the maximum peak inductor current command value ICONMAX and a slope compensation current ISLP. As shown in the example of FIG. 4, ISLP) can be subtracted from ICONMAX to determine the maximum inductor current level IL,PK,MAX, or
IL,PK,MAX=ICONMAX-ISLP.

At 520, the inductor current is sensed and the sensed inductor current ISNS is compared to (ICONMAX-ISLP). As shown in FIG. 4, the limit (ICONMAX-ISLP) is decreasing during the charging portion of the switching cycle and ISNS is increasing. The switching of the voltage converter circuit is enabled according to the comparison of ISNS and (ICONMAX-ISLP) at 525. When the sensed inductor current ISNS matches (ICONMAX-ISLP), the charging portion of the switching cycle ends, and the discharging portion of the switching cycle begins. Because the maximum peak inductor current command value ICONMAX varies with different values of output voltage (VOUT), the value of maximum peak inductor current value IL,PK,MAX when the switching cycle changes from charging to discharging is constant or flat for the different values of output voltage. Thus, a dynamic ICONMAX resolves the issue of reduced maximum peak inductor current discussed regarding FIGS. 3A and 3B, and achieves a Fixed Maximum Output Current Capability for the voltage converter.

FIG. 6 is a schematic of another example of a voltage regulator circuit 600. The schematic is similar to the schematic of FIG. 1. The circuit has a buck converter circuit topology and the switching circuit 110 adjusts a switching duty cycle to produce a regulated output voltage less than the input voltage. One difference from the circuit of FIG. 1, is that the voltage regulator circuit 600 of FIG. 6 includes a dynamic clamp circuit 630. The dynamic clamp circuit 630 includes a voltage to current (V/I) converter and produces a dynamic maximum peak inductor current command value ICONMAX or dynamic current clamp. Another difference is the oscillator circuit 614. In the example of FIG. 6, the oscillator circuit 614 generates a slope compensation current ISLP that has a dynamic slope instead of a fixed slope.

FIG. 7A is a block diagram of portions of an example of the dynamic clamp circuit 630 of FIG. 6. The dynamic clamp circuit 630 includes a voltage clamp circuit 732 and a V/I converter circuit 734. The inputs to the voltage clamp circuit 732 are the compensation voltage VC from the error amplifier circuit 112, the input voltage VIN, and the output voltage VOUT of FIG. 6. The output of the voltage clamp circuit 732 is a clamp voltage VC-CLP which is converted to the maximum peak inductor current command value ICONMAX.

FIG. 7B is a circuit diagram of an example of the voltage clamp circuit 732 of FIG. 7A. The voltage clamp circuit 732 modifies a base clamp voltage VCLAMP_BASE using a multiplier determined using VIN and VOUT. VCLAMP_BASE is determined by the desired IL,PK,MAX. The modified base clamp voltage is VCLAMP which is the sum of VCLAMP_BASE and VM. VM is the output of the multiplier circuit 738. To generate VM, the input and output voltages VIN and VOUT can be converted to input current and output current IIN and IOUT, respectively, using a second V/I converter 736. VM is the ratio (IOUT)2/(IIN). The compensation voltage VC and VCLAMP are then applied to comparator 740 to generate the dynamic maximum clamp voltage VC-CLP. The V/I converter circuit 734 of FIG. 7A then converts the dynamic maximum clamp voltage VC-CLP to the maximum peak inductor current command value ICONMAX. The slope compensation current ISLP is subtracted from ICONMAX to implement the improved slope compensation shown in FIG. 4.

Returning to FIG. 6, the oscillator circuit 614 generates a clock signal (CLK) and adjusts the duty cycle to produce the regulated output voltage VOUT. The oscillator circuit 614 also generates the slope compensation current ISLP according to the output voltage VOUT and the switching cycle TS. As explained previously herein, ISLP has a slope that is dynamic instead of fixed.

FIG. 8 is a circuit diagram of a clock circuit 842 and a slope current circuit 844. The clock circuit generates a voltage ramp signal VRAMP1 by charging a capacitor COSC with IOSC1 and generates the clock signal CLK using VRAMP1. FIG. 9 shows waveforms of the signals in the example of FIG. 8 including the VRAMP1, CLK, and the charging portion of the switching cycle TG. The switching cycle TS is determined from the charging of capacitor COSC and can be determined as
TS=(VREF_OSC*COSC)/IOSC1.
The top gate signal TG is determined by the switching circuit 110 in FIG. 1 from CLK and the output of comparator circuit 126.

The slope current circuit 844 includes two V/I converter circuits and a multiplier circuit 848. The first V/I converter 846 converts the output voltage VOUT to an output current IOUT. IOUT is used by multiplier circuit 848 to generate a charge current ISLP_CHG determined as
ISLP_CHG=(IOSC2*IOUT)/IREF,
where oscillator current IOSC2 and reference current IREF are DC currents to set the desired value of ISLP_CHG. Charge current ISLP_CHG charges capacitor CSLP to generate a slope compensation voltage (VRAMP2) as
VRAMP2=(ISLP_CHG/CSLP)*t.
FIG. 9 shows the waveform of VRAMP2. The second V/I converter 850 converts the slope compensation voltage to the slope compensation current ISLP.

FIG. 10 is a schematic of another example of a voltage regulator circuit 1000. The circuit has a boost converter circuit topology and the switching circuit 1010 adjusts a switching duty cycle to produce a regulated output voltage greater than the input voltage using an error signal from error amplifier 1012 representative of a difference between a target voltage value and the output voltage. The voltage regulator circuit 1000 includes a dynamic clamp circuit 1030 that produces a dynamic maximum peak inductor current command value ICONMAX, and an oscillator circuit 1014 that generates a slope compensation current ISLP that has a dynamic slope.

The dynamic clamp circuit 1030 is similar to the dynamic clamp circuit 630 of FIG. 6 except that it includes a voltage clamp circuit different from the voltage clamp circuit 732 shown in FIG. 7B. An example of a voltage clamp circuit for a boost converter circuit is shown in FIG. 11. Like the circuit in FIG. 7B, the voltage clamp circuit 1132 of FIG. 11 modifies a base clamp voltage VCLAMP_BASE using a multiplier. However, in FIG. 11 the output VM of the multiplier circuit 1138 is determined using an output current IOUT of the voltage regulator circuit and a difference between the input voltage and an output voltage (VOUT-VIN).

The VCLAMP_BASE is determined by the desired IL,MAX. The modified base clamp voltage is VCLAMP which is the sum of VCLAMP_BASE and VM. To generate VM, the output voltage VOUT is converted to output current IOUT using V/I converter circuit 1136. The difference between the input voltage and the output voltage (VOUT-VIN) is convened to a difference current IB=k*(VOUT-VIN), where k is a constant. The output of the multiplier VM is the ratio (IB)2/(IOUT).

The compensation voltage VC and the modified base clamp voltage VCLAMP are then applied to comparator circuit 1140 to generate the dynamic maximum clamp voltage VC-CLP. Another V/I converter circuit (e.g., V/I converter circuit 734 of FIG. 7A) converts the dynamic maximum clamp voltage VC-CLP to the maximum peak inductor current command value ICONMAX. The slope compensation current ISLP is then initialized from ICONMAX to implement the improved slope compensation shown in FIG. 4.

Returning to FIG. 10, the oscillator circuit 1014 generates the slope compensation current ISLP according to the output voltage VOUT, the input voltage VIN, and the switching cycle TS. As with the boost converter circuit example of FIG. 6. ISLP has a slope that is dynamic instead of fixed. FIG. 12 is a circuit diagram of a clock circuit 1242 and a slope current circuit 1244. The clock circuit 1242 is similar to the clock circuit 842 for the boost converter circuit in FIG. 8 and generates a voltage ramp signal VRAMP1 by charging a capacitor COSC with IOSC1, and generates the clock signal CLK using VRAMP1. The switching cycle TS is determined from the charging of capacitor COSC and can be determined as
TS=(VREF_OSC*COSC)/IOSC1.

The slope current circuit 1244 in FIG. 12 includes two V/I converter circuits and a multiplier circuit 1248. The first V/I converter circuit 1246 converts the difference between the input voltage and the output voltage (VOUT-VIN) to a difference current IA=kA*(VOUT-VIN), where kA is a constant. The difference current IA is used by multiplier circuit 1248 to generate the charge current ISLP_CHG determined as
ISLP_CHG=(IOSC2*IA)/IREF,
where oscillator current IOSC2 and reference current IREF are DC currents to set the desired value of ISLP_CHG. The first V/I converter circuit 1246 converts the output voltage VOUT to an output current IOUT. Charge current ISLP_CHG charges capacitor CSLP to generate a slope compensation voltage (VRAMP2) as
VRAMP2=(ISLP_CHG/CSLP)*t.
The second V/I converter 1250 converts the slope compensation voltage to the slope compensation current ISLP.

The slope compensation current ISLP is determined by the oscillator circuit 1214. ISLP is then subtracted from the maximum peak inductor current command value ICONMAX determined using the dynamic clamp circuit 1030. The difference (ICONMAX-ISLP) sets the maximum peak inductor current value IL,PK,MAX to implement the improved slope compensation of FIG. 4. The sensed inductor current ISNS is compared to IL,PK,MAX and the switching of the voltage regulator circuit 1000 is enabled according to the comparison. Again, this regulation with IL,PK,MAX occurs only under conditions in which a very high peak inductor current is needed at the load. Normally, the peak inductor current IL,PK is determined by the feedback to regulate the output voltage to the target voltage.

The method, circuits, and systems described herein enable stable operation of DC-DC converter circuits without sub-harmonic oscillation in the current limit condition. A dynamic maximum clamp limit and dynamic slope compensation control are combined to achieve a flat inductor current limit over the entire range of output voltage.

Additional Description and Aspects

Aspect 1 includes subject matter (such as a voltage regulator circuit) comprising a switching circuit, a dynamic clamp circuit, and a comparison circuit. The switching circuit adjusts a switching duty cycle to produce a regulated output voltage using an error signal representative of a difference between a target voltage value and the output voltage. The dynamic clamp circuit determines a maximum peak inductor current command value using the output voltage and an input voltage of the voltage regulator circuit. The comparison circuit sets a maximum peak inductor current value using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage; compares a sensed inductor current to a peak inductor current value, and enables switching of the voltage regulator system according to the comparison.

In Aspect 2, the subject flatter of Aspect 1 optionally includes a comparison circuit configured to set the maximum peak inductor current value to a difference between the slope compensation current and a maximum peak inductor current command value that varies with the different values of output voltage.

In Aspect 3, the subject matter of one or both of Aspects 1 and 2 optionally includes a dynamic clamp circuit configured to modify a base clamp voltage using a multiplier determined using the input voltage and the output voltage, and convert the modified the base clamp voltage to the maximum peak inductor current command value.

In Aspect 4, the subject matter of Aspect 3 optionally includes a dynamic clamp circuit configured to convert the input voltage and the output voltage to an input current and an output current, generate the multiplier using a ratio including the input current and the output current, generate the multiplier using a ratio including the input current and the output current, and convert the maximum clamp voltage to the maximum peak inductor current command value.

In Aspect 5, the subject matter of one or any combination of Aspects 1-4 optionally includes an oscillator circuit configured to determine the slope compensation current using the output voltage and a switching cycle.

In Aspect 6, the subject matter of Aspect 5 optionally includes an oscillator circuit including a first converter circuit configured to produce an output current from the output voltage, a multiplier circuit configured to generate a charge current using the output current, a capacitor coupled to the multiplier circuit to generate a slope compensation voltage using the charge current, and a second converter circuit configured to convert the slope compensation voltage to the slope compensation circuit.

In Aspect 7, the subject matter of one or any combination of Aspects 1-6 optionally includes switching circuit configured to adjust a switching duty cycle to produce a regulated output voltage less than the input voltage.

In Aspect 8, the subject matter of one or nay combination of Aspects 1-7 optionally includes a switching circuit configured to adjust timing of a charge portion and a discharge portion of the switching duty cycle using the comparison of the sensed inductor current and a peak inductor current value.

Aspect 9 can include subject matter (such as a method of operating a voltage regulator circuit) or can optionally be combined with one or any combination of Aspects 1-8 to include such subject matter, comprising receiving energy at the voltage regulator circuit and generating an output voltage according to a switching cycle, determining a maximum peak inductor current command value using the output voltage and an input voltage of the voltage regulator circuit, setting a maximum peak inductor current value of the voltage regulator circuit using the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage, comparing a sensed inductor current to a peak inductor current value, and enabling switching of the voltage regulator circuit according to the comparison.

In Aspect 10, the subject matter of Aspect 9 optionally includes subtracting the slope compensation current from a maximum peak inductor current command value that varies with the different values of output voltage to determine the maximum peak inductor current value that is constant for the different values of output voltage.

In Aspect 11, the subject matter of one or both of Aspects 9 and 10 optionally includes generating an output voltage less than an input voltage, modifying a base clamp voltage value using a multiplier determined using the input voltage and the output voltage, and converting the modified base clamp voltage value to the maximum peak inductor current command value.

In Aspect 12, the subject matter of one or any combination of Aspects 9-11 optionally includes determining the slope compensation current using the output voltage and the switching cycle.

In Aspect 13, the subject matter of Aspect 12 optionally includes generating a charge current using an output current of the voltage regulator system, charging a capacitor to generate a slope compensation voltage, and converting the slope compensation voltage to the slope compensation current.

In Aspect 14, the subject matter of one or any combination of Aspects 9-13 optionally includes generating an output voltage greater than an input voltage, modifying a base clamp voltage value using a multiplier determined using an output current of the voltage regulator system and a difference between the input voltage and the output voltage, and converting the modified base clamp voltage value to the maximum peak inductor current command value.

In Aspect 15, the subject matter of one or any combination of Aspects 9-14 optionally includes determining the slope compensation current using the output voltage, the input voltage, and the switching cycle.

In Aspect 16, the subject matter of Aspect 15 optionally includes generating a charge current using the difference between the input voltage and the output voltage, a reference current, and an oscillator current, charging a capacitor to generate a slope compensation voltage, and converting the slope compensation voltage to the slope compensation current.

Aspect 17 includes subject matter (such as a voltage regulator circuit) or can optionally be combined with one or any combination of Examples 1-16 to include such subject matter, comprising a switching circuit, a dynamic clamp circuit, and a comparison circuit. The dynamic clamp circuit determines a multiplier using an output current of the voltage regulator circuit and a difference between the input voltage and an output voltage, and modifies a base clamp voltage value using the multiplier to set a maximum peak inductor current command value.

In Aspect 18, the subject matter of Example 17 optionally includes a dynamic clamp circuit configured to convert the voltage difference between the input voltage and the output voltage to a difference current, generate the multiplier using the difference current, set a maximum peak clamp voltage using the base clamp voltage and the generated multiplier, and convert the maximum clamp voltage to the maximum peak inductor current command value.

In Aspect 19, the subject matter of one or both of Examples 17 and 18 optionally includes an oscillator circuit configured to determine the slope compensation current using the output voltage, the input voltage, and a switching cycle.

In Aspect 20, the subject matter of Aspect 19 optionally includes a first converter circuit configured to produce a difference current from a voltage difference between the output voltage and the input voltage, a multiplier circuit configured to generate a charge current using the difference current, a capacitor coupled to the multiplier circuit to generate a slope compensation voltage using the charge current, and a second converter circuit configured to convert the slope compensation voltage to the slope compensation circuit.

These non-limiting Aspects can be combined in any permutation or combination. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Method examples described herein can be machine or computer-implemented at least in part.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A voltage regulator circuit comprising:

a switching circuit configured to adjust a switching duty cycle to produce a regulated output voltage from an input voltage using an error signal representative of a difference between a target voltage value and the output voltage;
a dynamic clamp circuit configured to: convert the input voltage and the output voltage to an input current and an output current; generate a multiplier using a ratio including the input current and the output current; produce a maximum clamp voltage using a base clamp voltage and the generated multiplier; and convert the maximum clamp voltage to a maximum peak inductor current command value; and
a comparison circuit configured to: set a maximum peak inductor current value equal to a difference between the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage, and the maximum peak inductor current command value varies with the different values of output voltage; compare a sensed inductor current to a peak inductor current value; and enable switching of the voltage regulator system according to the comparison.

2. The voltage regulator circuit of claim 1, including an oscillator circuit configured to determine the slope compensation current using the output voltage and a switching cycle.

3. The voltage regulator circuit of claim 2, wherein the oscillator circuit includes:

a first converter circuit configured to produce an output current from the output voltage;
a multiplier circuit configured to generate a charge current using the output current;
a capacitor coupled to the multiplier circuit to generate a slope compensation voltage using the charge current; and
a second converter circuit configured to convert the slope compensation voltage to the slope compensation current.

4. The voltage regulator circuit of claim 1, wherein the switching circuit is configured to adjust the switching duty cycle to produce a regulated output voltage less than the input voltage.

5. The voltage regulator circuit of claim 1, wherein the switching circuit is configured to adjust timing of a charge portion and a discharge portion of the switching duty cycle using the comparison of the sensed inductor current and the peak inductor current value.

6. A method of operating a voltage regulator circuit, the method comprising:

receiving energy at the voltage regulator circuit and generating an output voltage according to a switching cycle;
converting an input voltage and the output voltage to an input current and an output current;
determining a multiplier using a ratio including the input current and the output current;
generating a modified base clamp voltage value using a base clamp voltage value and the multiplier;
converting the modified base clamp voltage value to a maximum peak inductor current command value;
setting a maximum peak inductor current value of the voltage regulator circuit equal to a difference between the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage and the maximum peak inductor current command value varies with the different values of output voltage;
comparing a sensed inductor current to a peak inductor current value, and
enabling switching of the voltage regulator circuit according to the comparison.

7. The method of claim 6,

wherein generating an output voltage according to a switching cycle includes generating an output voltage less than an input voltage.

8. The method of claim 7, including determining the slope compensation current using the output voltage and the switching cycle.

9. The method of claim 8, wherein determining the slope compensation current includes:

generating a charge current using an output current of the voltage regulator system;
charging a capacitor to generate a slope compensation voltage; and
converting the slope compensation voltage to the slope compensation current.

10. The method of claim 6,

wherein generating an output voltage according to a switching cycle includes generating an output voltage greater than an input voltage; and
wherein determining the multiplier includes:
determining the multiplier using an output current of the voltage regulator system and a difference between the input voltage and the output voltage.

11. The method of claim 10, including determining the slope compensation current using the output voltage, the input voltage, and the switching cycle.

12. The method of claim 11, wherein determining the slope compensation current includes:

generating a charge current using the difference between the input voltage and the output voltage, a reference current, and an oscillator current;
charging a capacitor to generate a slope compensation voltage; and
converting the slope compensation voltage to the slope compensation current.

13. A voltage regulator circuit comprising:

a switching circuit configured to adjust a switching duty cycle to produce a regulated output voltage greater than an input voltage using an error signal representative of a difference between a target voltage value and the output voltage;
a dynamic clamp circuit configured to:
determine a multiplier using an output current of the voltage regulator circuit and a difference between the input voltage and an output voltage; and
modify a base clamp voltage value using the multiplier to set a maximum peak inductor current command value;
an oscillator circuit including:
a first converter circuit configured to produce a difference current from a voltage difference between the output voltage and the input voltage;
a multiplier circuit configured to generate a charge current using the difference current;
a capacitor coupled to the multiplier circuit to generate a slope compensation voltage using the charge current; and
a second converter circuit configured to convert the slope compensation voltage to the slope compensation current; and
a comparison circuit configured to:
set a maximum peak inductor current value equal to a difference between the maximum peak inductor current command value and a slope compensation current, wherein the maximum peak inductor current value is constant for different values of output voltage and the maximum peak inductor current command value varies with the different values of output voltage;
compare a sensed inductor current to a peak inductor current value;
compare a sensed inductor current to a peak inductor current value; and
enable switching of the voltage regulator circuit according to the comparison.

14. The voltage regulator circuit of claim 13, wherein the dynamic clamp circuit is configured to:

convert the voltage difference between the input voltage and the output voltage to a difference current;
generate the multiplier using the difference current;
set a maximum peak clamp voltage using the base clamp voltage and the generated multiplier; and
convert the maximum peak clamp voltage to the maximum peak inductor current command value.
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Patent History
Patent number: 11070132
Type: Grant
Filed: Jun 7, 2019
Date of Patent: Jul 20, 2021
Patent Publication Number: 20200389091
Assignee: Analog Devices International Unlimited Company (Limerick)
Inventors: Hai Chen (Gilbert, AZ), Gregory J. Hughes (Paradise Valley, AZ)
Primary Examiner: Fred E Finch, III
Assistant Examiner: Kevin H Sprenger
Application Number: 16/435,039
Classifications
Current U.S. Class: Switched (e.g., Switching Regulators) (323/282)
International Classification: H02M 3/158 (20060101); G05F 1/62 (20060101); H02M 1/00 (20060101);