Fin-based device having an isolation gate in physical contact with a source/drain
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
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The present application is a continuation of U.S. application Ser. No. 16/218,578, filed on Dec. 13, 2018, which is a continuation of U.S. application Ser. No. 15/784,335, filed on Oct. 16, 2017, which is a divisional of U.S. application Ser. No. 14/334,842, filed on Jul. 18, 2014, each of which is hereby incorporated herein by reference in its entirety.
BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, has been introduced to replace a planar transistor. Although existing semiconductor devices and methods of fabricating semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, to introduce three dimensional nanostructure to a gate channel raises challenges in a semiconductor device process development. It is desired to have improvements in this area.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure is directed to, but not otherwise limited to a metal-oxide-semiconductor field-effect transistor (MOSFET), for example a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present invention. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.
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One or more long contacts may be configured to extend along the second direction 194 and to extend over the first active region 106 and the second active region 108. The long contacts have a first dimension extending along the first direction 192 and a second dimension extending along the second direction 194, and the first dimension is substantially shorter than the second dimension. The one or more long contacts may be used to electrically connect the doped regions of two adjacent gates on both the first active region 106 and the second active region 108. For example, a long contact 122 may be used to electrically connect doped source regions of the gate 111 and the gate 112 extending over the first active region 106 and the second active region 108. A long contact 125 may be used to electrically connect doped source regions of the gate 113 and the gate 114 extending over the first active region 106 and the second active region 108.
One or more gate contacts 128-130 may also be formed on the corresponding gates for routing the gates to the metal routing lines (not shown) correspondingly. The metal routing lines may be formed in one or more metal layers (not shown) on the gates.
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For further clarification,
According to some embodiments of the present disclosure, an interlayer dielectric (ILD) layer 218 may be formed on the source/drain features 208 as shown in
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In some embodiments, the materials, formation, and layout of the dielectric layer 212 and/or the material layer 224 may also be designed such that, a controlled bias voltage may be applied to the isolation gate 224 for effective isolation between the circuit 131 and the circuit 132.
In some embodiments, the trench 222 may also be filled by a dielectric layer. The dielectric layer may be formed using similar method(s) and/or similar material(s) as those for the dielectric layer 212 as discussed previously. For example, the dielectric layer may include one or more materials selected from the group consisting of LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), HfO2, BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, and silicon oxynitride (SiON). The dielectric layer used to fill the trench 222 may include any suitable materials, such as silicon oxide, silicon nitride, silicon carbide, and/or silicon oxynitride. In some examples, the dielectric layer may be deposited to fully fill the trench 222 to provide sufficient electrical isolation property. In some embodiments when the isolation gate 224 includes a dielectric material filled in the trench 222, the dielectric material used to fill in the trench 222 is different from the materials used to form the sidewall spacers 216 formed along the isolation gate 224. In some examples, the dielectric layer may partially fill the trench 222. For example a lower portion of the trench 222 may be filled by the dielectric layer, and an upper portion of the trench 222 may be filled by the dielectric layer 212 and the material layer 224. The dielectric layer filled in the lower portion of the trench 222 may have similar function(s) as that of the isolation region (STI) to separate the circuit 131 and the circuit 132. The dielectric layer may be formed by ALD, PVD, CVD, or other suitable process.
Referring to
-
- 1. isolation gate poly removing and trench etch,
- 2. dielectric deposition (re-fill the isolation gate), and
- 3. functional gate formation (which may further include removing the poly gate, high-K gate dielectric, work-function metal, and the low resistance metal formation.)
Referring to
At process 502, the MOSFET device precursor, e.g., the FinFET device precursor 200 is provided. In some embodiments, the MOSFET device precursor includes a substrate, and one or more fins formed in a first active region and a second active region over the substrate. The one or more fins may be separated by one or more isolation regions. One or more gates may be formed over the one or more fins and extending over the first active region and the second active region. The one or more gates may be formed to extend along a direction that is substantially perpendicular to a direction along which the one or more fins may be formed to extend. Source/drain features may be formed in source/drain regions of the MOSFET device precursor.
At process 504, an ILD layer is deposited over the surfaces of each of the fins. The ILD layer may include silicon oxide, silicon oxynitride, or other suitable dielectric materials. The ILD layer may include a single layer or multiple layers. The ILD layer may be formed by a suitable technique, such as CVD, ALD, and spin-on dielectric, such as SOG. A CMP process may be performed to provide a planar top surface of the ILD layer.
At process 506, a dummy polygate may be removed to form a trench disposed between two adjacent circuits. The dummy polygate may be removed using any appropriate lithography and etching processes. The etching processes may include selective wet etch or selective dry etch. After removing the dummy polygate, one or more active fin lines in the active regions are revealed. In some embodiments, the lithography process may include forming a photoresist layer (resist), exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element including the resist. As shown in
At process 508, the trench may be further recessed using the ILD layer as etching mask elements. The remained spacer sidewalls may also be used as mask elements to recess the trench. For example as shown in
At process 510, one or more material layers may be deposited in the recessed trench to form an isolation gate between the two adjacent circuits. In some embodiments, the isolation gate may include a multiple layered structure of IL/HK/MG. In some embodiments, the isolation gate may include a dielectric material fully filled in the recessed trench. In some embodiments, the isolation gate may include a dielectric material filling a lower portion of the recessed trench, and an IL/HK/MG structure filling an upper portion of the recessed trench. The isolation gate may be formed to electrically isolate the two adjacent circuits. The one or more material layers may be formed using ALD, PVD, CVD, or other suitable process.
It is understood, however, that the present disclosure should not be limited to a particular type of device, except as specifically claimed. For example, the present disclosure is also applicable to other MOSFET device. It is also understood that additional steps can be provided before, during, and after the method, and some of the steps described can be replaced or eliminated for other embodiments of the method.
The present embodiments describe structures and methods for forming MOSFET devices using a self-aligned etching process to form an isolation gate for sufficient electrical isolation between adjacent transistors. The mechanisms involve using the remained ILD layer and the spacer sidewalls as etching mask elements to form a trench in the MOSFET device. One or more materials layers may then be deposited to fill the trench to provide sufficient electrical isolation between adjacent circuits. The mechanisms provide a lithography friendly patterning process with improved overlay control without using advanced lithography tools. Thus, no extra cost or area penalty is needed in the present embodiments. The mechanisms may also provide a fully balance source/drain epitaxial growth environment, which may improve device stability, chip speed, cell matching performance, and reduce standby specification. The various embodiments of the present disclosure may achieve an improved uniformity control on source/drain regions, and a fully uniform fin-end allocation for both reliability and process margin improvement.
The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
The present disclosure provides a fin-like field-effect transistor (FinFET) device comprising a substrate including a first active region and a second active region spaced apart from each other in a first direction; a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction; one or more gates configured to extend over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and at least one functional gate; sidewall spacers formed on sides of the one or more gates; source/drain features formed on sides of the sidewall spacers; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the one or more gates. A first height of the first isolation gate is substantially greater than a second height of sidewall spacers formed on sides of the first isolation gate.
The present disclosure provides a method of forming a semiconductor device comprises providing a device precursor including a substrate including a first active region and a second active region spaced apart from each other in a first direction; a first group of fins configured in the first active region, and a second group of fins configured in the second active region, each of the first group of fins and the second group of fins extending along a second direction substantially perpendicular to the first direction; and one or more gates including a polygate configured to extend over the first active region and the second active region, each of the one or more gates extending along the first direction. The polygate is configured to separate a first circuit and a second circuit. The method further comprises depositing an interlayer dielectric (ILD) layer over the substrate; removing the polygate to form a trench; recessing the trench to the substrate using the ILD layer as etching mask elements; and depositing one or more material layers in the recessed trench to form an isolation gate between the first circuit and the second circuit.
The present disclosure provides a method of forming a semiconductor device comprising forming a first group of fins in an n-well region and a second group of fins in a p-well region on a substrate; forming one or more isolation features to separate adjacent fins of the first group of fins and the second group of fins; forming one or more gates including a polygate on the first group of fins and the second group of fins, the polygate configured to separate a first circuit and a second circuit; forming sidewall spacers along the polygate; forming source/drain features on the substrate and on two sides of the polygate; depositing an interlayer dielectric (ILD) layer on the source/drain features; removing the polygate to form a trench between the first circuit and the second circuit; recessing the trench using the ILD layer as etching mask elements to a depth lower than bottoms of the source/drain features to form a V-shaped trench; and depositing one or more material layers in the V-shaped trench to form an isolation gate between the first circuit and the second circuit.
In some embodiments, the recessing the trench further comprises: using the ILD layers and the sidewall spacers along the polygate as etching mask elements.
In some embodiments, the depositing the one or more material layers includes depositing interfacial layer (IL)/high-k (HK) dielectric layer/metal gate (MG) in the V-shaped trench.
In some embodiments, the depositing the one or more material layers includes depositing a dielectric layer in the V-shaped trench.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A device comprising:
- a fin structure disposed over a substrate;
- an isolation gate and a first gate structure disposed over the fin structure; and
- a source/drain feature disposed in the fin structure adjacent the isolation gate, and
- wherein the isolation gate includes a high-k dielectric layer and a conductive layer, the high-k dielectric layer extending into the fin structure such that the high-k dielectric layer physically contacts the source/drain feature and the fin structure, the conductive layer extending into the fin structure to a first depth and the source/drain feature extending into the fin structure to a second depth, the first depth being greater than the second depth.
2. The device of claim 1, wherein the high-k dielectric layer extends into the fin structure to a third depth that is greater than the first depth.
3. The device of claim 1, wherein the first gate structure is a functional gate structure that is associated with the source/drain feature.
4. The device of claim 1, wherein the first gate structure is another isolation gate that includes another conductive layer and another high-k dielectric layer, wherein the another conductive layer of the another isolation gate extends along an edge of the fin structure to a third depth that is less than the first depth.
5. The device of claim 1, wherein the first gate structure extends to a first height over the fin structure and the isolation gate extends to the first height over the fin structure.
6. The device of claim 5, wherein the first gate structure is disposed on the fin structure without extending into the fin structure.
7. The device of claim 1, further comprising a second gate structure disposed over the fin structure on a first side of the isolation gate,
- wherein the first gate structure is disposed over the fin structure on a second side of the isolation gate, the second side being opposite the first side,
- wherein the first gate structure is part of a first circuit and the second gate structure is part of a second circuit, and
- wherein the isolation gate isolates the first circuit from the second circuit.
8. A device comprising:
- a semiconductor fin structure disposed over a substrate;
- a first gate and a first isolation gate disposed over the semiconductor fin structure;
- a first source/drain feature disposed within the semiconductor fin structure on a first side of the first isolation gate and extending into the semiconductor fin structure to a first depth;
- a second source/drain feature disposed within semiconductor fin structure on a second side of the first isolation gate, the second side being opposite the first side; and
- wherein the first isolation gate includes a dielectric layer and a conductive layer, the dielectric layer extending into the semiconductor fin structure such that the dielectric layer physically contacts the first source/drain feature and the second source/drain feature, the conductive layer extending into the semiconductor fin structure to a second depth that is greater than the first depth.
9. The device of claim 8, wherein the conductive layer includes a first portion having a first width and a second portion having a second width that is different than the first width.
10. The device of claim 9, wherein the first portion of the conductive layer is disposed above the semiconductor fin structure and the second portion of the conductive layer is disposed within the semiconductor fin structure.
11. The device of claim 8, further comprising a sidewall spacer disposed along and interfacing with the dielectric layer of the first isolation gate.
12. The device of claim 8, further comprising:
- a second gate disposed over the semiconductor fin structure;
- a first sidewall spacer disposed along a first sidewall of the second gate; and
- a second sidewall spacer disposed along a second sidewall of the second gate, the second sidewall being opposite the first sidewall, wherein the first sidewall spacer is longer than the second sidewall spacer measured in a direction that is substantially perpendicular to the substrate.
13. The device of claim 12, further comprising a dielectric isolation structure disposed on the substrate, and
- wherein the first sidewall spacer interfaces with the dielectric isolation structure and the second sidewall spacer interfaces with the semiconductor fin structure.
14. The device of claim 8, wherein the second source/drain feature extends into the semiconductor fin structure to the first depth.
15. The device of claim 8, wherein the conductive layer includes a metal gate layer.
16. A device comprising:
- a semiconductor fin structure disposed over a substrate;
- a first gate, a first isolation gate and a second isolation gate disposed over the semiconductor fin structure; and
- a first source/drain feature associated with the first isolation gate and extending into the semiconductor fin structure to a first depth; and
- wherein the first isolation gate includes a dielectric layer and a conductive layer, the dielectric layer extending into the semiconductor fin structure such that the dielectric layer physically contacts the first source/drain feature and the semiconductor fin structure, the conductive layer extending into the semiconductor fin structure to a second depth that is greater than the first depth and the second isolation gate extending along an outer edge of the semiconductor fin structure to a third depth that is different than the first depth and the second depth.
17. The device of claim 16, further comprising a dielectric isolation structure disposed on the substrate, and
- wherein the second isolation gate interfaces with the dielectric isolation structure.
18. The device of claim 16, wherein the second isolation gate includes another dielectric layer and another conductive layer, and
- wherein the another dielectric layer extends to the third depth, and
- wherein the another conductive layer extends along the outer edge of the semiconductor fin structure to a fourth depth that is less than the third depth.
19. The device of claim 18, further comprising:
- a first sidewall extending along the dielectric layer of the first isolation gate to a fourth depth, and
- a second sidewall extending along the another dielectric layer to a fifth depth that is greater than the fourth depth.
20. The device of claim 16, wherein the first isolation gate, the second isolation gate and the first gate all extend to the same height above the substrate, and
- wherein the first gate is disposed on the semiconductor fin structure without extending into the semiconductor fin structure.
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Type: Grant
Filed: Aug 3, 2020
Date of Patent: Mar 1, 2022
Patent Publication Number: 20200365590
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsin-Chu)
Inventor: Jhon Jhy Liaw (Hsinchu County)
Primary Examiner: Younes Boulghassoul
Application Number: 16/983,914
International Classification: H01L 27/092 (20060101); H01L 29/06 (20060101); H01L 29/49 (20060101); H01L 29/51 (20060101); H01L 29/165 (20060101); H01L 21/8234 (20060101); H01L 21/8238 (20060101); H01L 21/28 (20060101); H01L 21/306 (20060101); H01L 21/308 (20060101); H01L 21/762 (20060101); H01L 29/66 (20060101);