With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) Patents (Class 257/401)
  • Patent number: 11031295
    Abstract: Embodiments of the present invention are directed to a gate cap last process for forming a self-aligned contact. This gate cap last process allows for a thin SAC cap, as the SAC cap only needs to prevent a short between the metallization contact and the gate. In a non-limiting embodiment of the invention, a gate is formed over a channel region of a fin. The gate can include a gate spacer. A sacrificial contact is formed on a top surface of a source or drain (S/D) region of a substrate. The sacrificial contact is positioned directly adjacent to a sidewall of the gate spacer. An exposed surface of the gate is recessed to form a recessed gate surface and a self-aligned contact (SAC) cap is formed on the recessed gate surface. The sacrificial contact is replaced with a S/D contact.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Choonghyun Lee
  • Patent number: 11031384
    Abstract: Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-su Kim
  • Patent number: 11031389
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to semiconductor structures disposed over active regions, more particularly, via contact structures disposed over such active regions and to methods of forming such semiconductor structures.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Hui Zang
  • Patent number: 11024713
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Glenn A. Glass, Harold W. Kennel, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 11024546
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 11024715
    Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 1, 2021
    Assignee: Tessera, Inc.
    Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
  • Patent number: 11018260
    Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yao-Jen Yang, Yih Wang
  • Patent number: 11004724
    Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
  • Patent number: 11004774
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 11, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 10998239
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate. The semiconductor device structure also includes an insulating structure that includes a first insulating layer formed between and separating from the first fin and the second fin, a second insulating layer embedded in the first insulating layer, a first capping layer formed in the first insulating layer to cover a top surface of the second insulating layer, and a second capping layer in the first capping layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 10991811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10991813
    Abstract: A method for fabricating a semiconductor device is carried out so that silicon nanowires may be made of vertically stacked one or more floating silicon layers, and a silicon buffer layer may be surrounded on each surface of the silicon nanowires with a sufficient thickness, e.g., close to the diameter of the nanowire, and then a silicon germanium shell may be formed on it. Thus, a semiconductor device having a silicon germanium shell channel structure can be fabricated with a uniform thickness even on a bulk silicon substrate using a conventional silicon CMOS process.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 27, 2021
    Inventors: Seongjae Cho, EunSeon Yu
  • Patent number: 10985069
    Abstract: A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee
  • Patent number: 10978471
    Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Patent number: 10978583
    Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 13, 2021
    Assignee: Cree, Inc.
    Inventors: Yueying Liu, Saptharishi Sriram, Scott Sheppard, Jennifer Gao
  • Patent number: 10971590
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate having interior surfaces that define a trench within an upper surface of the substrate. One or more dielectric materials are disposed within the trench. A source region disposed within the substrate and a drain region is disposed within of the substrate and separated from the source region along a first direction. A gate structure is over the upper surface of the substrate between the source region and the drain region. The upper surface of the substrate has a first width directly below the gate structure that is larger than a second width of the upper surface of the substrate within the source region or the drain region. The first width and the second width are measured along a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 10971403
    Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
  • Patent number: 10971606
    Abstract: A method for manufacturing a semiconductor device includes forming a shallow trench isolation (STI) structure surrounding a pair of semiconductor fins; forming a dummy gate layer over the STI structure and the semiconductor fins; etching a first portion of the dummy gate layer to form a trench through the dummy gate layer until the STI structure is exposed, in which the trench extends between the semiconductor fins along a lengthwise direction of the semiconductor fins; forming an insulating structure in the trench through the dummy gate layer; after forming the insulating structure extending through the dummy gate layer, patterning the dummy gate layer to form a pair of dummy gate structures each of which is across a respective one of the semiconductor fins; and replacing the dummy gate structures with a pair of metal gate structures.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 10971628
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature over a substrate and a fin structure protruding from the substrate and partially surrounded by the isolation feature. The fin structure includes a first portion above the isolation feature and having a first width. The fin structure also includes a second portion extending from a top of the first portion and having a second width greater than the first width, so that the fin structure above the isolation feature has a T-shaped profile. The semiconductor device structure also includes a gate structure covering the first portion and the second portion of the fin structure.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Neng Lin, Shian-Wei Mao
  • Patent number: 10971593
    Abstract: A p-type FinFET has an oxygen reservoir disposed on the gate stack. The oxygen reservoir provides an oxygen rich environment during processing steps of manufacturing the device to help the work function metal retain or obtain oxygen to maintain or increase the work function and keep the Vth of the device lower.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang
  • Patent number: 10971626
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Patent number: 10971405
    Abstract: A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: April 6, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10964706
    Abstract: A 3-D IC includes a substrate having a substrate surface. A first semiconductor device has a first electrical contact and is formed in a first area of the surface on a first plane substantially parallel to the substrate surface. A second semiconductor device has a second electrical contact and is formed in a second area of the surface on a second plane substantially parallel to the surface and vertically spaced from the first plane in a direction substantially perpendicular to the surface. A first electrode structure includes opposing top and bottom surfaces substantially parallel to the substrate surface, and a sidewall connecting the top and bottom surfaces such that the electrode structure forms a three dimensional electrode space.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 30, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton J. deVilliers
  • Patent number: 10964818
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Yong Li
  • Patent number: 10957695
    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Barn Chen, Chi-Cherng Jeng, Shiu-Ko Jangjian, Ting-Huang Kuo
  • Patent number: 10957639
    Abstract: An electronic component includes a part incorporating a transistor provided with a control electrode and with first and second electrodes. The electronic component includes first, second, and third electrical connection terminals extending on a connection face of the part incorporating the transistor, the first electrical connection terminal being electrically linked with the first electrode, the second electrical connection terminal being electrically linked with the second electrode and the third electrical connection terminal being electrically linked with the control electrode. The electronic component includes a first set of electrically conductive fingers and a second set of electrically conductive fingers, the fingers of the first and second sets of fingers being interdigitated, at the level of the connection face, to form at least a part of a capacitive component. The fingers of the first set of fingers are electrically linked to the first electrical connection terminal.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit Thollin, Thibault Catelain
  • Patent number: 10950736
    Abstract: Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: March 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Joanne Huang, Jamil Kawa
  • Patent number: 10950490
    Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau
  • Patent number: 10950692
    Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ruilong Xie, Vimal Kamineni, Shesh Mani Pandey, Hui Zang
  • Patent number: 10943818
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10943915
    Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Albert Fayrushin, Haitao Liu, Kirk D. Prall
  • Patent number: 10943904
    Abstract: An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-seong Lee, Ju-youn Kim, Ji-hoon Yoon, Il-ryong Kim, Kyoung-hwan Yeo, Jae-yup Chung
  • Patent number: 10943988
    Abstract: A semiconductor device includes epitaxially grown source/drain (S/D) regions each having a cross-sectional quadrilateral shape formed on a semiconductor fin on opposite sides of a transversely disposed gate structure. The S/D regions include top (111) facets on top halves of the cross-sectional quadrilateral shape. The device further includes a silicide formed on the top (111) facets.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10943827
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate. A top surface of the first fin structure is closer to the semiconductor substrate than a top surface of the second fin structure. The semiconductor device structure also includes a first epitaxial structure on the first fin structure. The semiconductor device structure further includes a second epitaxial structure on the third fin structure. The first epitaxial structure is wider than the second epitaxial structure.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chun Keng, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 10943831
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10943911
    Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • Patent number: 10937894
    Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wei-Yang Lee, Chih-Shan Chen
  • Patent number: 10930781
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Patent number: 10930668
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Patent number: 10930765
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a semiconductor fin on the substrate, forming a dummy gate structure on the semiconductor fin, forming a first dielectric layer on the semiconductor structure exposing an upper surface of the dummy gate structure, removing the dummy gate structure and a portion of the semiconductor fin below the dummy gate structure to form a trench that divides the semiconductor fin into a first portion and a second portion spaced apart from each other, and forming a second dielectric layer on the semiconductor structure filling the trench. The method provides a semiconductor device having a non-recessed trench isolation structure.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 23, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10930795
    Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen, Carlos H Diaz
  • Patent number: 10930740
    Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-in Jung, Moon-young Jeong, Joon Han, Satoru Yamada
  • Patent number: 10922467
    Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: February 16, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Bohai Liu, Gang Ni, Chunlei Zhu, Gary K. Yeap
  • Patent number: 10923565
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Patent number: 10910370
    Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 2, 2021
    Inventors: Seung Hyun Song, Young Chai Jung
  • Patent number: 10910373
    Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Se-wan Park, Baik-Min Sung, Bo-Cheol Jeong
  • Patent number: 10910496
    Abstract: A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yang Lo, Tung-Wen Cheng
  • Patent number: 10910277
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 10903335
    Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 26, 2021
    Assignee: IMEC VZW
    Inventors: Gaspard Hiblot, Sylvain Baudot, Hans Mertens, Julien Jussot
  • Patent number: 10903239
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu