With Specified Physical Layout (e.g., Ring Gate, Source/drain Regions Shared Between Plural Fets, Plural Sections Connected In Parallel To Form Power Mosfet) Patents (Class 257/401)
  • Patent number: 11404321
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming sacrificial gate stacks over the substrate; forming a sacrificial fill layer over the sacrificial gate stacks; removing the sacrificial fill layer; forming sidewall spacers besides the sacrificial gate stacks; removing the sacrificial gate stacks; and forming metal gate stacks; wherein the sacrificial fill layers is made of fill materials with a high etch rate selectivity to materials of the sidewall spacers.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Sheng Huang, Ryan Chia-Jen Chen
  • Patent number: 11404553
    Abstract: A semiconductor device includes a source/drain region, a body region, a first gate structure, and a second gate structure. The source/drain region and the body region are in a substrate. The first and second gate structures are above the substrate. The source/drain region and the body region are on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source/drain region, the body region, and the first gate structure are on a same side of the second gate structure.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 2, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xin-Yong Wang, Liu Han
  • Patent number: 11398559
    Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jyun Huang, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 11398449
    Abstract: A semiconductor device includes a semiconductor chip having an electrode pad, a terminal having a terminal pad, and a bonding wire. The bonding wire includes a first end portion, a first bonded portion bonded to the electrode pad, a loop portion extending between the semiconductor chip and the terminal, and a second bonded portion bonded to the terminal pad. The second bonded portion is a wedge bonded portion comprising a second end portion of the bonding wire opposite to the first end portion. A length of the first bonded portion in the first direction is greater than a length of the second bonded portion in the first direction.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 26, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazuya Maruyama, Tsutomu Sano
  • Patent number: 11393814
    Abstract: A method for forming a semiconductor device includes: forming a semiconductor fin extending upwardly from a substrate; breaking the semiconductor fin into two separate fin structures; conformally forming a first dielectric layer over the fin structures; after conformally forming the first dielectric layer, filling a recess between the fin structures with a first flowable oxide; etching back the first flowable oxide to lower a top surface of the first flowable oxide to a level below top surfaces of the fin structures; conformally forming a second dielectric layer over the first dielectric layer and the etched back first flowable oxide, such that a laterally portion of the second dielectric layer in the recess is lower than the top surfaces of the fin structures; planarizing the first and second dielectric layers to expose the fin structures, while leaving the laterally portion of the second dielectric layer covering the first flowable oxide.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 11393900
    Abstract: In an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Han Chen, Tsung-Ju Chen, Chun-Heng Chen, Chi On Chui
  • Patent number: 11387229
    Abstract: Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeha Lee, Ha-Young Kim, Bonghyun Lee, Soyoung Lee, Yongeun Cho
  • Patent number: 11387340
    Abstract: A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger. The gate bond pad extends on the gate finger and/or the drain bond pad extends on the drain finger.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 12, 2022
    Assignee: WolfSpeed, Inc.
    Inventors: Frank Trang, Zulhazmi Mokhti, Haedong Jang
  • Patent number: 11387237
    Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11380768
    Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11373909
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The semiconductor device includes a plurality of fin-shaped active regions spaced apart from each other in the device region and extending in a first direction. The semiconductor device includes a protruding pattern extending along a bottom surface of the trench. Moreover, an interval between the protruding pattern and the plurality of fin-shaped active regions is greater than an interval between two adjacent ones of the plurality of fin-shaped active regions.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 28, 2022
    Inventors: Sung-Min Kim, Dong-won Kim, Geum-jong Bae
  • Patent number: 11374024
    Abstract: Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Gilbert Dewey, Willy Rachmady, Anh Phan
  • Patent number: 11362187
    Abstract: A semiconductor device includes first and second active regions on a substrate, an element isolation layer between the first and second active regions, a dummy gate line, dummy gate spacers at opposite side walls of the dummy gate line, and a dummy gate capping layer on the dummy gate line and. An upper surface of the element isolation layer is proximate to an upper surface of the substrate in relation to an upper end of the first active region in a vertical direction. The dummy gate line includes a horizontal section extending on the first active region to the element isolation layer in a horizontal direction, and a vertical section extending downwards from the horizontal section along a side wall of the first active region, the dummy gate line having an L shape, a vertical thickness of the horizontal section being smaller than a vertical thickness of the vertical section.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juyoun Kim, Jinwoo Kim, Kyuman Hwang
  • Patent number: 11355641
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 11355396
    Abstract: The present disclosure provides a method of forming a semiconductor structure with a metal gate. The semiconductor structure is formed by first fabricating fins over a semiconductor substrate, followed by a formation of a source and a drain recess. A source and a drain region may then be deposited into the source and the drain recess. The gate structure may be deposited into the region between the fins. The gate structure includes dielectric and metallic layers. In the regions between the fins, the gate structure is isolated from the source and the drain region by an insulating layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Shi Ning Ju, Chih-Hao Wang, Kuan-Ting Pan
  • Patent number: 11355608
    Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar
  • Patent number: 11349027
    Abstract: The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11348916
    Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey, Orb Acton, Willy Rachmady
  • Patent number: 11348803
    Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 31, 2022
    Assignee: Applied Materials, Inc.
    Inventor: Byeong Chan Lee
  • Patent number: 11342455
    Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Sin Wang, Shan-Yun Cheng, Ching-Hung Kao, Jing-Jyu Chou, Yi-Ting Chen
  • Patent number: 11342445
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11342328
    Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Guyoung Cho, Subin Shin, Donghyun Roh, Byung-Suk Jung, Sangjin Hyun
  • Patent number: 11335776
    Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Wang, Pei-Hsun Wang
  • Patent number: 11335604
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen, Kai-Tai Chang
  • Patent number: 11335705
    Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Brian S. Doyle, Ravi Pillarisetty, Abhishek A. Sharma, Elijah V. Karpov
  • Patent number: 11329042
    Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Lien Jung Hung, Shih-Hao Lin
  • Patent number: 11329647
    Abstract: In a communication system, a communication terminal device transmits and receives RF signals frequently. Subsequent to an antenna of the communication terminal device, the communication terminal device includes a radio frequency switch (also referred to as transmit/receive (T/R) switch) that switches between two states at a high frequency, where one state is for receiving RF signal and other state for transmitting RF signal. In the exemplary embodiments of the disclosure, a complementary metal-oxide-semiconductor (CMOS) switch is provided, where the CMOS switch is deigned to have a high reliability by coupling a body of a transistor of the CMOS switch to a bias voltage through a switch, where the insertion loss and isolation are improved for the operation of the CMOS switch.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Garming Liang, En-Hsiang Yeh
  • Patent number: 11329163
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai
  • Patent number: 11322618
    Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 11322614
    Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Dong Woo Kim, Sang Moon Lee, Seung Hun Lee
  • Patent number: 11315836
    Abstract: A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11309417
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Mark van Dal, Martin Christopher Holland, Gerben Doornbos
  • Patent number: 11302636
    Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungyoung Lee, Sanghoon Baek
  • Patent number: 11302612
    Abstract: A lead frame wiring structure including first and second bonding parts positioned apart from each other, and a coupling part extending in a first direction to couple the first and second bonding parts. The coupling part includes a coupling face section, and first and second leg sections extending respectively from two opposite end portions of the coupling face section toward the first and second bonding parts. The first bonding part includes a wide section having a side edge portion and a peripheral section adjacent to the side edge portion in a second direction, and a narrow section protruding in the first direction from the side edge portion. In the coupling part, the coupling face section is spaced apart from the two bonding parts in a third direction, and the first leg section is connected to the peripheral section of the first bonding part. The first to third directions are perpendicular to one another.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 12, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryo Maruyama
  • Patent number: 11302693
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Shi-Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11296200
    Abstract: A semiconductor device including one or more transistors is disclosed. The semiconductor device includes a first active region disposed over a well region of a substrate, a plurality of dummy active regions disposed around the first active region, and a gate disposed to traverse the first active region, wherein a portion of the gate is disposed to overlap with at least one of the plurality of dummy active regions and is electrically coupled to the at least one of the plurality of dummy active regions.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Kil Seo
  • Patent number: 11289606
    Abstract: A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shi Ning Ju, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Wen-Ting Lan
  • Patent number: 11282836
    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deepak Sharma, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
  • Patent number: 11282936
    Abstract: Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
  • Patent number: 11276609
    Abstract: A semiconductor structure and a method for forming the same, and a transistor are provided. In one form, a method includes: providing a base, where a dummy gate layer is formed on the base, a spacer is formed on a side wall of the dummy gate layer, an interlayer dielectric layer is formed on the base exposed from the dummy gate layer and the spacer, and the interlayer dielectric layer exposes a top of the dummy gate layer and a top of the spacer; removing a portion of a height of the dummy gate layer to form a remaining dummy gate layer, where the remaining dummy gate layer and the spacer enclose a trench; thinning a spacer exposed from the remaining dummy gate layer along a direction perpendicular to a side wall of the trench; after the thinning, removing the remaining dummy gate layer to form a gate opening within the interlayer dielectric layer; and forming a metal gate structure in the gate opening. Through the thinning, a gate opening whose side wall is provided with a remaining spacer is T-shaped.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 15, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11270987
    Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Mog Park, Sang Youn Jo
  • Patent number: 11264385
    Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11264480
    Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 11264268
    Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MTAIWANANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chang-Ta Yang
  • Patent number: 11264270
    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11264502
    Abstract: A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11264277
    Abstract: A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Pokuan Ho, Hsin-Ping Chen, Chia-Tien Wu
  • Patent number: 11264486
    Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Hao Chu, Chia-Chung Chen, Shu Fang Fu, Chi-Feng Huang, Victor Chiang Liang
  • Patent number: 11257718
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 22, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Chanro Park, Stan Tsai
  • Patent number: 11257943
    Abstract: A semiconductor device includes a semiconductor substrate having a drift region, and an edge terminal structure portion provided between the active region and an end portion of the semiconductor substrate on an upper surface of the semiconductor substrate. The edge terminal structure portion includes a plurality of guard rings of a second conductivity type which are in contact with the upper surface, and a high concentration region of the first conductivity type which has a higher doping concentration than the drift region and is provided, between adjacent two of the guard rings, from a position shallower than lower ends of the guard rings to a position deeper than the lower ends of the guard rings. Each of the guard rings has a region that is not covered by the high concentration region as viewed from a lower surface side.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Soichi Yoshida