Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.

Abstract: One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.

Abstract: A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

Abstract: A semiconductor device includes a substrate, first and second fins over the substrate and extending upwardly in a first direction, an epitaxial material comprising a first portion, a second portion, and a third portion, and a conductive feature in contact with the epitaxial material. The first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions. The third portion has a bottom surface bended upwardly with an apex located between the first and second fins. In a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, the bottom surface has a first straight line and a second straight line intersecting at the apex.

Abstract: In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.

Abstract: Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a radio-frequency switching device can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the radio-frequency switching device.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first dielectric fin and a second dielectric fin over a substrate, and the second dielectric fin is taller than the first dielectric fin. The method also includes forming a gate stack over the substrate, and the gate stack extends across the first dielectric fin and the second dielectric fin. The method further includes partially removing the gate stack such that an opening exposing the second dielectric fin is formed and forming an isolation structure in the opening.

Abstract: A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first portion of an oxide layer around the dummy contact structure, performing a second etching process to at least partially remove the first portion of oxide layer, forming a spacer layer around the dummy contact structure, performing a second deposition process to form a second portion of the oxide layer around the spacer layer, removing the spacer layer and the dummy contract structure to leave an opening, and filling the opening with a conductive material to form a conductive plug.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: The present disclosure provides a semiconductor device and a semiconductor layout structure. In the semiconductor device, a guard ring of a first type is arranged on at least one side of a transistor of a second type, and a guard ring of a second type is arranged on at least one side of a transistor of a first type, such that a plurality of signal lines in a first metal layer in the semiconductor layout structure may be arranged between a first power source line and a first ground line. Furthermore, in a second metal layer, a plurality of second power source lines are connected to one first power source line, and a plurality of second ground lines are connected to one first ground line.

Abstract: A device includes gate spacers over a substrate, and a gate structure between the gate spacers. The gate structure includes an interfacial layer over the substrate, a metal oxide layer over the interfacial layer, a metal oxide layer over the interfacial layer, a first metal nitride layer over the metal oxide layer, a second metal nitride over the first metal nitride layer, and a tungsten-containing material interposing the first metal nitride layer and the second metal nitride layer.

Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.

Abstract: At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.

Abstract: A semiconductor device according to an embodiment of the present inventive concept includes a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having one or more gate structures and one or more active regions, and in some standard cells providing the same circuit and in standard cell regions at different locations, input lines or/and output lines are at different locations.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having self-aligned isolation structures. The present disclosure provides self-aligned isolation fins that can be formed by depositing dielectric material in openings formed in a spacing layer or by replacing portions of fins with dielectric material. The self-aligned isolation fins can be separated from each other by a critical dimension of the utilized photolithography process. The separation between self-aligned isolation fins or between the self-aligned isolation fins and active fins can be approximately equal to or larger than the separations of the active fins.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A semiconductor device a method of forming the same are provided. The semiconductor device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure.

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.

Abstract: A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: An integrated circuit includes a strip structure having a front side and a back side. The integrated circuit includes a gate structure on the front side of the strip structure. The integrated circuit includes an isolation structure surrounding the strip structure. The integrated circuit includes a backside via in the isolation structure. The integrated circuit includes a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and in contact with the backside via.

Abstract: A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

Abstract: Zero expanded functional gate structures are formed by utilizing a dipole material spacer as a means to prevent expanded void formation during a replacement metal gate process. Notably, the dipole material spacer prevents expanded void formation into the dielectric spacer thus preventing the functional gate structures from being in direct physical contact with the source/drain regions. Improvement in yield loss and reliability is thus provided utilizing a dipole material spacer during a replacement metal gate process.

Abstract: Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern.

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FIN FET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract: A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first and second gate spacers formed over a semiconductor substrate, longitudinally extending along a first direction, and separated from each other by a gate electrode layer. A first insulating layer longitudinally extends along a second direction to pass through the gate electrode layer and the first and second gate spacers. A gate dielectric layer has a top surface covered by the gate electrode layer. The top width of the gate dielectric layer is less than that of the gate electrode layer. The first and second gate spacers and the first insulating layer have first, second and third hydrophobic surfaces, respectively. These hydrophobic surfaces are in direct contact with first, second and third sidewall surfaces of the gate electrode layer, respectively.

Abstract: A semiconductor structure and method for fabricating a semiconductor structure includes using two separate oxide layers to improve device reliability. A first oxide layer is formed adjacent a fin (e.g. a fin of a fin field-effect transistor (FinFET) device), a dummy gate is formed adjacent the first oxide layer, the dummy gate is removed, and a second oxide layer is then formed adjacent the first oxide layer. The use of the second oxide layer can improve device reliability by covering any damage that may be inflicted on the first oxide layer when the dummy gate is removed.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure, a semiconductor structure and a memory. The method of manufacturing a semiconductor structure includes: forming a first semiconductor layer on a substrate, the first semiconductor layer including a first trench region and a to-be-doped region on two opposite sides of the first trench region; forming a word line, the word line surrounding a sidewall surface of a part of the first semiconductor layer in the first trench region, and at least a part of a projection of a part of the first semiconductor layer in the to-be-doped region on a surface of the substrate coinciding with a projection of the word line on the surface of the substrate; forming a doping body portion, the doping body portion including first dopant ions.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.