Polishing method for selective chemical mechanical polishing of semiconductor substrates

Abstract

A chemical mechanical polishing method is provided for polishing substrates with one or more barrier layers on an underlying dielectric layer utilizing a polishing composition with a high selectivity for removal of the barrier layer material (for e.g. tantalum) resulting in a substrate with a planar dielectric layer with minimal scratching and erosion.

Description

[0001] The invention relates to a method for removing one or more barrier layers from an underlying dielectric layer by chemical mechanical polishing (CMP) while minimizing removal of the underlying dielectric layer and without damaging the underlying dielectric layer by scratching or erosion.

[0002] U.S. Pat. No. 5,676,587 discloses a method for removing a barrier layer, referred to as a liner film, by performing a first polishing step that is stopped purposely before the polishing step has reached the underlying dielectric layer, to avoid scratching of the underlying dielectric layer, followed by a second polishing step that uses a neutral pH, silica-based slurry that selectively attacks the material of the barrier layer and not the underlying dielectric layer, such that removal by polishing is substantially faster for the barrier layer than for the dielectric layer.

[0003] U.S. Pat. No. 5,876,490 discloses a method for polishing a surface having elevated portions (referred to as plateaus) and recessed portions (referred to as valleys). The slurry used during polishing contains both uncoated abrasives and poly-ion coated abrasives. The poly-ion coated abrasives climb up and accumulate in the recessed portions perpendicular to the direction of shear, thereby reducing abrasion of the recessed portions, such that removal by polishing is significantly faster for the elevated portions than for the recessed portions on the same surface.

[0004] Embodiments of this invention are illustrated by way of example with reference to the attached drawings.

[0005] FIG. 1 shows a typical semiconductor substrate with a metal layer, a barrier layer and an underlying oxide layer.

[0006] FIG. 2 shows a typical semiconductor substrate with the metal layer removed and the barrier layer exposed.

[0007] FIG. 3 shows a typical polished semiconductor substrate utilizing the method of this invention to remove the barrier layer thereby resulting in a planar oxide surface with minimal erosion of the oxide layer.

[0008] CMP is an enabling technology for the production of complex and dense semiconductor structures on semiconductor substrates and is an effective method for the removal and planarization of thin films on semiconductor substrates during the production of integrated circuits including multi-chip modules, capacitors and the like.

[0009] The “damascene” process is employed for forming interconnect lines and vias for multi-layer metal structures that provide the “wiring” of an integrated circuit and involves etching a trench in a planar dielectric (insulator) layer and filling the trench with a conductive material. The conductive material is typically a metal such as aluminum, copper, or tungsten. A technique called “dual-damascene” adds etched vias for providing contact to the lower level as the damascene structure is filled. Typically a layer of another material is first deposited to line the trenches and vias to prevent the migration of metal ions into the dielectric layer. This migration barrier or barrier layer (also referred to as a liner layer) typically comprises tantalum, tantalum nitride, titanium and/or titanium nitride. One or more barrier layers may be provided depending on the specific application. More details are found in “Making the Move to Dual Damascene Processing,” Semiconductor International, August 1997.

[0010] In known CMP, the semiconductor substrate to be polished is mounted on a carrier or polishing head of a polishing machine. The exposed surface of the substrate is placed against a rotating polishing pad. The surface of the polishing pad that is in contact with the semiconductor substrate is referred to as the polishing layer. The polishing pad may be a standard pad (without any abrasive in the polishing layer) also referred to herein as the non fixed-abrasive pad or a fixed-abrasive pad (containing abrasive in the polishing layer). The carrier head provides a controllable pressure (or downforce), on the substrate to bias it towards the polishing pad. A polishing fluid with or without abrasive particles is then dispensed at the interface of the wafer and the polishing pad to enhance removal of the target layer (for e.g., metal layer in first-step CMP or barrier layer in second-step CMP). The polishing fluid is preferably water based and may or may not require the presence of abrasive particles, depending on the composition of the polishing layer of the polishing pad. An abrasive-free polishing fluid also referred to as a reactive liquid is typically used with a fixed-abrasive pad while a polishing fluid containing abrasive particles is typically used with a non fixed-abrasive pad. For polishing softer metal interconnects, such as copper, the polishing fluid can contain up to 3% by weight of abrasive particles. Typical abrasives used in CMP of semiconductor substrates include alumina, silica, ceria, germania, titania, zirconia, diamond, boron nitride, boron carbide, silicon carbide and combinations thereof. Preferably, the composition used with the method of this invention contains abrasive particles made of colloidal silica.

[0011] Material removal from the substrate surface is due to: friction between the polishing pad and the substrate and mechanical action of the abrasive particles in the slurry resulting in wear of the substrate; and chemical interaction of other slurry constituents with the substrate. Thus, the rate of material removal from the substrate surface is determined by the applied pressure, the velocity of pad rotation, and slurry constituents. The polishing rates or material removal rates are increased by adding constituents to the slurries which are corrosive to the substrate. These constituents typically comprise chemicals that are oxidizing agents, complexing agents, acids and/or bases. The complexing agents also act as dispersants. Typical complexing agents include malic acid, gluconic acid, glycolic acid, citric acid, phthalic acid, pyrocatechol, pyrogallol, gallic acid, tannic acid and the like. Preferably complexing agents are present up to about 5.0%, yet more preferably from about 0.1 to 1.0% by weight of the slurry. Typical oxidizing agents include hydrogen peroxide, iodates such as potassium iodate, nitrates such as cesium nitrate, barium nitrate, ammonium nitrate, mixtures of ammonium nitrate and cesium nitrate, carbonates such as ammonium carbonate, persulfates such as ammonium and sodium sulfate and perchlorates. Preferably oxidizing agents are present at about 1 to about 15% by weight, and more preferably from about 5 to about 10% by weight of the slurry. The polishing composition also contains pH buffers, surfactants, deflocculants, viscosity modifiers, wetting agents, cleaning agents and the like.

[0012] Constituents are also added to ensure selective removal of one material over the other. In an embodiment of this invention, nitrogen-containing polymeric compounds are used to suppress the dielectric layer removal rate thereby resulting in preferential removal of one or more barrier layers with minimal scratching and erosion of the underlying dielectric layer. The ratio of barrier material removal rate to dielectric removal rate is termed the barrier:dielectric selectivity ratio, also referred to herein for the sake of brevity as Ta:TEOS selectivity ratio. To make the CMP process effective for barrier layer removal, it is desirable to keep this ratio as high as possible while minimizing erosion of the underlying dielectric layer and any dishing of conductive material in vias or trenches.

[0013] One problem prevalent throughout the polishing industry is the unwanted removal of dielectric from the substrate during polishing (i.e., oxide erosion or loss). A number of methods have been shown to minimize dielectric material removal rates during CMP. It is thus desirable to minimize or eliminate dielectric removal while still providing acceptable barrier removal rates in the final polishing step of any CMP process.

[0014] The method of this invention is used to selectively remove a barrier or liner layer comprised of one or more layers of suitable barrier materials from an underlying dielectric layer (e.g., silicon oxide or silicon oxide derived from tetraethyl orthosilicate(TEOS)) with minimal erosion of the dielectric layer. Materials suitable for use in the barrier layer include titanium, tantalum, titanium nitride, tantalum nitride or alloys thereof. In an embodiment, the method of this invention preferably utilizes a polishing composition comprising a nitrogen-containing polymer for the selective removal of barrier layer from an underlying dielectric layer.

[0015] FIG. 1 illustrates a cross-section of a typical semiconductor substrate with a conductive material layer 10, a barrier layer 11 with an underlying dielectric layer 12 on a semiconductor substrate 13. The dielectric layer 12 typically has openings (vias or trenches) 14 that are filled with the conductive material to provide a path through the dielectric layer to previously deposited layers. The conductive material is typically copper, tungsten, aluminum, metal silicide, doped polysilicon and the like. The barrier layer is typically silicon oxide or silicon oxide derived from TEOS, silicon nitride, silicon oxynitride, low-k dielectrics with siloxane bridges and the like.

[0016] FIG. 2 shows a cross-section of the semiconductor substrate of FIG. 1 with the conductive metal layer removed resulting in the exposed surface 21 of the barrier layer. Known polishing compositions designed to polish and planarize the conductive material layer 10 are used to obtain the exposed barrier layer surface 21 with a via 22 containing conductive material.

[0017] FIG. 3 shows a cross-section of the semiconductor substrate of FIG. 2 wherein the barrier layer 21 has been selectively removed utilizing the method of this invention to obtain a planar dielectric surface 31 with a via 32 containing conductive material.

[0018] In an embodiment, the method of this invention is performed with a slurry that contains abrasive particles at about 0.0001, 0.05, 0.1, 0.25, 0.5, 1, 2, 3, 4, 5, 10, 15, 20, 25, to 30% by weight slurry. The method of this invention is preferably performed with a slurry that contains colloidal silica particles. It has been found that abrasives with more uniform particle size provide greater oxide erosion protection. Preferably, the method of this invention is performed utilizing a slurry with substantially all abrasive particles having a mean size less than 5&mgr;. Substantially as used herein is intended to mean at least 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 99.5, 99.9% of the colloidal silica particles are less than about 5&mgr;.

[0019] In an embodiment, the method of this invention utilizes an aqueous polishing composition comprising colloidal silica particles, an inhibitor, a dispersant, a biocide and a nitrogen-containing polymeric compound. The nitrogen-containing polymeric compound is preferably polyethyleneimine (PEI) with a molecular weight preferably from about 100, 200, 500, 600, 700, 800, 900, 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10,000, 20,000, 30,000, 40,000, 50,000, 100,000, 200,000, 300,000, 400,000, 500,000, 600,000, 700,000 to about 1,000,000, more preferably from about 800 to about 50,000, yet more preferably from about 500 to about 10,000 and most preferably from about 500 to about 1000. In an embodiment, the polyethyleneimine is a mixture of relatively high-molecular weight (from about 100 to about 5,000) and even higher molecular weight (from about 5,000 to about 1,000,000) polyethyleneimines to obtain a number average molecular weight in a range of about 500 to about 1000. The abrasive particles are preferably colloidal silica. The inhibitor is typically added to prevent dishing of conductive material in any vias on the semiconductor substrate. In substrates with copper as the conductive material, the inhibitor used is typically an azole such as benzotriazole, tolyltriazole or mixtures thereof. The inhibitor is typically added at a concentration of about 50, 100, 200, 300, 400, 500, 1000, 2000, 3,000 or 5,000 ppm (parts per million by weight of the slurry). Other exemplary inhibitors that are used include: 1-hydroxybenzotriazole,N-(1H-benzotriazole-1-ylmethyl)formamide, 3,5dimethylpyrazole, indazole, 4-bromopyrazole, 3-amino-5-phenyl pyrazole, 3-amino-4-pyrazolecarbonitrile, 1-methyimidazole, Indolin QTS and the like. The biocide used is preferably Neolone M50 available from Rohm and Haas Co. with an active ingredient of 5-chloro-2-methyl-4-isothiazolin-3-one.

[0020] In a preferred embodiment, the method of this invention is utilized on a substrate wherein the dielectric layer is made of silicon dioxide. The hydrated silicon dioxide surface has silanol and siloxane groups wherein the siloxane (Si—O—Si) linkage is formed by self condensation of silanol (Si—OH) groups. The silanol group is characterized by high acidity and thus has a tendency to form strong hydrogen bonds with organic molecules containing suitable hydrogen bonding sites (also referred to as electron donor sites). Thus, the dielectric layer removal rate can be suppressed by the addition of suitable organic molecules that contain multiple functional groups that strongly interact through hydrogen bonding with the hydrated dielectric layer surface.

[0021] In a preferred embodiment, the method of this invention is performed utilizing a slurry that contains organic molecules that exhibit a strong affinity for the dielectric layer. These organic molecules have functional groups that are capable of forming strong intermolecular hydrogen bonds with silanol groups on the hydrated dielectric layer surface. Preferably the organic molecules are derived from nitrogen-containing organic compounds such as polyacrylamide, polyvinylpyrrolidone, and polyethyleneimine, yet more preferably polyethyleneimine. In a preferred embodiment, the organic molecule is a polyethyleneimine having a molecular weight of about 500, 600, 700, 800, 900, 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10,000, 20,000, 30,000, 40,000, 50,000, 100,000, 200,000, 300,000, 400,000, 500,000, 600,000, 700,000 to about 1,000,000, more preferably from about 800 to about 50,000, yet more preferably from about 500 to about 10,000 and most preferably from about 500 to about 1000. The nitrogen atoms in polyethyleneimine form strong intermolecular hydrogen bonds with the silanol groups (for e.g. SiOH . . . N) on the dielectric layer surface thus suppressing the oxide removal rate. Polyethyleneimines have a general chemical structure as follows:

(—NH—CH2—CH2—)m(—N(CH2—CH2—NH2)—CH2—CH2—)n

[0022] wherein m and n are integers that can be varied independently of each other, with each having a value greater than or equal to 1.

[0023] Branched polyethyleneimines have a general chemical structure as follows:

H2N—(—CH2—CH2—NR—)m—(—CH2—CH2—NH—)n—

[0024] where R is (—CH2—CH2—N—) and m and n are each greater than or equal to 1, respectively.

[0025] The multiple nitrogen atoms in respective polymeric molecules such as polyethyleneimine serve as sites for intermolecular hydrogen bonds with the silanol and siloxane groups on the dielectric surface resulting in the formation of a strong protective film on the dielectric surface thereby minimizing material removal from the dielectric surface. Thus, organic molecules each with multiple nitrogen atoms provide multiple electron donor sites capable of forming stronger intermolecular hydrogen bonds with silanol and siloxane groups on the dielectric surface than do organic molecules with single electron donor sites. Examples of molecules with single donor sites are lower molecular weight amines, imidazole, phenol, glycol and other compounds indicated in U.S. Pat. No. 5,614,444.

[0026] Thus, the method of this invention can be used for the selective removal of one or more barrier layers with minimal erosion of silicon dioxide in the dielectric layer. Embodiments of this invention are described by the following examples which are not meant to restrict the scope of this invention and are provided only to illustrate the method of this invention.

EXAMPLE 1

[0027] A polishing composition according to this invention was used to polish Copper, TEOS and Tantalum wafers. An IPEC 472 polisher was used with a slurry flow rate of 200 ml/min. Each formulation contained a surfactant at about 0.2% by weight, a biocide (Neolone M50 obtained from Rohm and Haas Company, based in Philadelphia, Pa.) at a concentration of about 0.01% by weight; Benzo triazole (BTA) at about 0.1% by weight; and Klebesol 1501-50 (obtained from Clariant Corp) at about 8.5% by weight of the polishing composition. The removal rates observed with the various formulations are listed in the following table. 1 Ta:TEOS Sample TEOS RR Ta RR Selectivity No. PEI (800) PEI (50K) PEI (750K) pH (A/min) (A/min) Ratio 1 — — — 7 729 400 0.5:1 2 — — — 11 715 400 0.55 3 0.25 — — 11 11 298 27.1:1 4 — 0.68 — 11 122 462 3.8:1 5 — 0.2  — 11 33 387 11.7:1 (See 1 below) 6 — — 0.2 11 50 200 4:1 Note: (1) This data set was obtained using an AMAT Mirra Polishing Machine with an IC1010 polishing pad (available from Rodel, Inc. based in Newark, Delaware) with a downforce of 3 psi, a carrier speed of 103 rpm, a slurry flow rate of 200 ml/min and a polishing time of 60 seconds.

[0028] Slurry formulation 3 containing polyethyleneimine with an average molecular weight of 800 was most selective for barrier layer removal.

Claims

1. A method for selectively removing one or more barrier layers from a semiconductor substrate containing an underlying dielectric layer, comprising the steps of:

providing a substrate having a barrier layer requiring removal;

providing a polishing pad;

biasing said substrate and said polishing pad under a fixed pressure; and

dispensing a polishing composition at an interface between the substrate and the polishing pad thereby removing the barrier layer;

wherein said polishing composition has as a constituent, a polymer having at least two functional groups forming intermolecular hydrogen bonds with silanol and siloxane groups on said dielectric layer thereby suppressing removal of the dielectric layer.

2. The method of claim 1 performed on a substrate containing one or more barrier layers wherein said barrier layer is made of a material selected from a group consisting of tantalum, tantalum nitride, titanium, titanium nitride or combinations thereof.

3. The method of claim 2 performed with said polishing composition having an alkaline pH in a range of about 7 to 11, comprising:

abrasive particles;

an inhibitor;

a dispersant;

a biocide; and

a nitrogen-containing polymeric compound.

4. The method of claim 3 performed with said polishing composition containing up to about 30% by weight colloidal silica wherein the nitrogen-containing polymeric compound is selected from a group consisting of polyacrylamides and polyethyleneimines.

5. The method of claim 4 wherein the method is performed with a polishing composition containing a polyethyleneimine with an average molecular weight in a range of about 500 to about 1000.

6. The method of claim 5 wherein the method is performed with a polishing composition containing a mixture of low-molecular weight polyethyleneimines and high molecular weight polyethyleneimines such that the number average molecular weight of said mixture is in a range of about 500 to 1,000.

7. The method of claim 6 wherein the method is performed with a polishing composition wherein said inhibitor is an aromatic triazole selected from a group consisting of benzotriazole, tolyltriazole or mixtures thereof.

8. The method of claim 5 wherein the method is performed with a polishing composition wherein said inhibitor is an aromatic triazole selected from a group consisting of benzotriazole, tolyltriazole or mixtures thereof.

9. A method of polishing by CMP using abrasives and a polishing fluid to remove a barrier layer from an underlying dielectric layer, comprising:

polishing the barrier layer while using a polishing composition having as a constituent, organic molecules having at least two functional groups forming intermolecular hydrogen bonds with silanol groups on the dielectric layer, said organic molecules resisting removal of the dielectric layer during polishing.