Trench transistor and method for fabricating a trench transistor with high-energy-implanted drain

Abstract

The invention relates to a method for fabricating a trench transistor, in which there are formed, within an epitaxial layer (11, 11′) deposited above a substrate (10) of a first conductivity type (n), a trench (14) and, within the trench (14), a gate dielectric (15) and a gate electrode (16) and, in a body region (20) of a second conductivity type (p) adjoining the trench (14) a source region (13) of the first conductivity type (n), a drift region (12) of the first conductivity type (n) forming a drain zone being formed at the end of the junction between the substrate (10) and the epitaxial layer (11, 11′) by means of one or more high-energy implantations, the lower end (U) of the trench (14) projecting into said drift region (12), and to a trench transistor of this type formed as a low-voltage transistor.

Description

The invention relates to a trench transistor and also to a method for fabricating a trench transistor, in which there are formed, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and, in a body region of a second conductivity type adjoining the trench a source region of the first conductivity type.

A trench transistor of this type and a method of this type are disclosed in U.S. Pat. No. 5,814,858 A.

An important aim in the development of new generations of DMOS power transistors is reducing the on resistivity R_on·A. This makes it possible, on the one hand, to minimize the static power loss, and, on the other hand, it is possible to achieve higher current densities. Since the on resistance increases with the maximum drain voltage of a transistor, it is endeavored to manage with lower drain voltages. The specific capacitances responsible for the switching losses are only slightly dependent on the maximum drain voltage, thus resulting in smaller transistors with lower capacitances and lower switching losses.

Usually, for fabricating n-channel DMOS transistors, an n⁻-type epitaxial layer is deposited on a low-impedance n⁺-type substrate, the lower part of said epitaxial layer forming the drift path. The body region is produced by redoping the epitaxial region. In order to reduce the maximum drain voltage and the on resistivity of such a DMOS transistor, usually the drift path is doped more highly and the length of the drift path is simultaneously reduced. For a maximum drain voltage of less than approximately 20 V, the doping of the drift path may become higher than the doping of the body region. However, the transistor can then no longer be fabricated according to the prior art because a reproducible redoping of the more highly doped epitaxial region is not possible.

In order to solve the above difficulties, there is a proposal, for realizing DMOS transistors having a relatively low maximum drain voltage, to deposit a p-type epitaxial layer on an n⁺-type substrate, said epitaxial layer forming the body region. The drain region is formed by the substrate. In this case, however, the thickness of the epitaxial region is controlled very imprecisely, and the outdiffusion of the substrate varies with the doping concentration thereof, with the result that the channel length is subjected to major fluctuations and the on resistance R_on of the transistor thus fluctuates greatly. Furthermore, there is the proposal to deposit a two-stage epitaxial layer, the bottommost layer of which is n-doped and the top layer of which is p-doped. In the abovementioned U.S. patent specification, for fabricating a low-voltage MOSFET trench transistor, in order to reduce the deviations of the breakdown voltage and of the on resistance that are caused by the thickness variations of the epitaxial layer, use is made of a high-energy implantation for definition of the drain region. However, in that case the junction between the epitaxial region and the substrate is defined by the implantation of a buried layer and an n-type epitaxial layer is used. Finally, in the U.S. patent specification, high doses of 1×10¹⁴ cm⁻² or more are required for implantation of the buried layer, with the result that the high implantation is not used for definition of the channel length. Furthermore, a certain thickness of the n-type epitaxial layer remains between the top side of the buried layer and the underside of the p-type body.

It is an object of the invention to specify a fabrication method for a trench transistor designed for a low maximum drain voltage and a trench transistor of this type in which it is possible to set more precisely the channel length by means of a high-energy implantation and also the doping of the drift region that forms the drain region.

This object is achieved in accordance with the claims.

In accordance with a first aspect of the invention, the above object is achieved by means of a method for fabricating a trench transistor, in which there are formed, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and, in a body region of a second conductivity type adjoining the trench a source region of the first conductivity type, a drift region of the first conductivity type forming a drain zone being formed at the end of the junction between the substrate and the epitaxial layer by means of one or more high-energy implantations, the lower end of the trench projecting into said drift region.

Consequently, the invention likewise proposes a high-energy implantation for definition of the drain region. However, in the case of this invention, the drift region which is formed by the high-energy implantation and defines the drain zone sets the junction between the body region and the epitaxial region and thus the channel length. Moreover, this invention uses an epitaxial layer which is doped with the second conductivity type (for example p) or else an undoped epitaxial layer, in one case the epitaxial layer forming the later body region without redoping, while in a second case the body region is formed by a redoping by means of implantation and, if appropriate, diffusion of the epitaxial layer.

In one embodiment, the drift region, the body region and the source region of the vertical trench transistor may be formed prior to the formation of the trench. In an alternative embodiment, the drift region, the body region and the source region of the vertical trench transistor may be formed after the formation of the trench and the filling thereof with the gate dielectric and the gate electrode. A preceding planarization, for example by filling with oxide to above the surface and subsequent CMP, is then advisable. The dose proposed by the invention for the high-energy implantation of the drift region is approximately 10¹² cm⁻².

The trench transistor fabricated according to the invention is particularly characterized by the fact that the doping of the drift region is higher than the doping of the body region.

In accordance with a second aspect, the invention, in order to achieve the above object, enables a trench transistor having, within an epitaxial layer deposited above a substrate of a first conductivity type, a trench and, within the trench, a gate dielectric and a gate electrode and also, in a body region of a second conductivity type adjoining the trench, a source region of the first conductivity type, the trench transistor furthermore having: a drift region of the first conductivity type which forms a drain zone, extends from the end of the junction between the substrate and the epitaxial layer beyond the lower end of the trench and directly adjoins the underside of the body region, the drift zone being doped more highly than the body zone.

In a preferred exemplary embodiment, the first conductivity type forms the n type and the second conductivity type forms the p type.

The above and further advantageous features of a method according to the invention for fabricating a trench transistor and also of a trench transistor according to the invention are described in more detail below in exemplary embodiments with reference to the accompanying drawing.

FIG. 1 shows a diagrammatic cross section of the trench transistor known from the document cited in the introduction;

FIGS. 2A-2D show individual fabrication steps of a first exemplary embodiment of the method according to the invention in the form of diagrammatic cross sections;

FIGS. 3A-3E show individual fabrication steps of a second exemplary embodiment of a fabrication method according to the invention in the form of diagrammatic cross sections;

FIG. 4 graphically shows a simulated characteristic by way of example of the absolute values of the net doping concentrations of two trench transistors according to the invention in each case with a higher and a lower maximum drain voltage, and

FIG. 5 graphically shows profile characteristics of the doping concentration of three trench transistors according to the invention with differently dosed high-energy drain implantation in comparison with the absolute values of the net doping of a trench transistor with a p-type epitaxial layer without high-energy drain implantation.

FIG. 1 illustrates the structure of a low-voltage trench transistor known from the document cited in the introduction, in the form of a diagrammatic cross section. In this case, a buried n⁺-type layer 2 (buried layer) is formed by means of a high-energy implantation in an n-type epitaxial layer 3 lying above an n⁺-type substrate 1. Redoping of the n-type epitaxial layer 3 produces a p-type body region 4, in the surface of which n⁺-type source regions 7 are situated. A trench 5 passes down into the buried n⁺-type layer 2 and a gate dielectric 9 and a gate electrode 6 are formed in the trench. Finally, the source region 7 is contact-connected by a source electrode 8, while the substrate 1 is contact-connected by a drain electrode (not shown). In the case of this trench transistor designed for low drain voltages, the junction between the epitaxial layer 3 and the substrate 1 is defined by the buried n⁺-type layer. Moreover, in the case of this known trench transistor, the high-energy implantation of the buried n⁺-type layer 2 is effected with doses of 1×10¹⁴ cm⁻² or more. In the case of the known trench transistor illustrated diagrammatically in FIG. 1, a region of the n-type epitaxial layer 3 that is not affected by the high-energy implantation is additionally situated between the buried n⁺-type layer 2 and the p-type body 4.

It shall be mentioned here that the various embodiments of the fabrication method according to the invention and of the proposed trench transistor which are described in the description below and are illustrated in FIGS. 2 to 5 are related by way of example to n-channel trench transistors but are not restricted thereto. In the case of the fabrication steps of a first exemplary embodiment of a fabrication method according to the invention which are described in detail with reference to FIGS. 2A-2D, firstly a p-type epitaxial layer 11 is deposited on an n⁺-type substrate 10, said epitaxial layer forming the later body region without redoping. At the end of the epitaxial region/substrate junction, an n-type drift region is formed by redoping the p-type epitaxial region by means of one or more high-energy implantations if appropriate having a different dosage (FIG. 2A). An n⁺-type source region 13 is formed in the body region 20 in the p-type epitaxial layer 11 by implantation and, if appropriate, diffusion (FIG. 2B). Afterward, in accordance with FIG. 2C, a trench 14 is introduced through the source region 13 and the body region 20 right into the drift region 12. In other words, the bottom U of the trench 14 extends right into the drift region 12. Afterward, in accordance with FIG. 2D, a gate dielectric 15 and a gate electrode 16 are formed in the trench 14 and the source region 13 (and, if appropriate, the body region 20) is contact-connected to a source electrode 17 and the substrate 10 is contact-connected to a drain electrode 18.

The channel length indicated by an arrow C in FIG. 2D is set according to the invention, according to the text above, by means of the n-type drift region 12 introduced by high-energy implantation and, if appropriate, diffusion.

In comparison with FIG. 1 illustrating the trench transistor of the prior art, it is noticeable in FIG. 2D that, in the case of the trench transistor according to the invention, the upper boundary of the n-type drift region 12 directly adjoins the lower boundary of the p-type body region 20 and thereby unambiguously defines the channel length C. It should additionally be mentioned that the doping of the n-type drift region, that is to say of the drain zone 12, which is achieved by means of the high-energy implantation, may be higher than the doping of the p-type body region 20, which is to be realized for a low-voltage trench transistor (for example for a drain voltage of 15 V) (cf. FIGS. 4 and 5).

Whereas a p-doped epitaxial layer 11 was formed in the case of the fabrication steps illustrated with reference to FIGS. 2A-2D, an undoped epitaxial layer (or p-type or n-type epitaxial layer that is lightly doped in comparison with the dopant concentrations of the finished component) 11′ is deposited on the substrate 10 in the case of the second exemplary embodiment, defined by the fabrication steps illustrated in FIGS. 3A-3E. The p-type body region 20 is formed by an implantation and, if appropriate, diffusion before or after the high-energy implantation that is used to form the n-type drift region 12 and is illustrated in FIG. 3A. As a result, the dopant concentration of the body region 20 can be set much more accurately than by epitaxial growth. FIGS. 3C-3E correspond to the method steps illustrated in FIGS. 2C and 2D and are not explained in any greater detail here.

In further variants of the method according to the invention, the drift region 12, the body region 20 and the source region 13 may be introduced before or after the etching of the trench 14. Particularly if the high-energy implantation that is used to form the drift region 12 is performed after the etching of the trench 14, the surface which is not at the same level as the mesa (that is the zone situated next to the trench) may have the effect that the implanted ions experience a different deceleration in the trench than in the mesa and that the implantation peak lies at a different depth which is then subjected to the variations of, in particular, the “poly-recess”. It is advantageous, therefore, to carry out the implantation of the drain or drift region 12 before the trench 14 is actually etched. However, excessively high temperature budgets are then no longer permitted to occur or it is necessary to use dopants that diffuse as slowly as possible for implantation of the drain or drift region.

As an alternative to this, the high-energy implantation is carried out after the etching of the trench 14 and the introduction of oxide and electrode into the trench 14. A preceding planarization of the surface for example by filling with oxide to above the surface and subsequent CMP is then ideal.

FIG. 4 graphically shows the profile characteristic of the doping concentration against the depth of the trench transistor specified in micrometers. The absolute value of the net concentration is plotted logarithmically. The profile characteristic proceeds from the source region illustrated on the left over the body region and the drift region to the substrate situated on the right, which starts approximately at a depth of 3 to 4 μm. The solid curve shows the profile characteristic of a 25 V trench transistor in accordance with the prior art, while the dashed curve shows the profile characteristic of a trench transistor designed for a maximum drain voltage of 15 V. In this case, the dashed curve shows that the doping of the drift region is higher than that of the body region. The lower boundary of the body region and the upper boundary of the drift region coincide at the depth of 1 μm, where they define the end of the channel.

FIG. 5, which is a graphical illustration similar to FIG. 4, shows in dotted fashion the net doping of a trench transistor with a p-type epitaxial layer without high-energy drain implantation (curve O). Uninterrupted curves I, II, III show the profile characteristic of the doping concentration (logarithmic) of a low-voltage trench transistor according to the invention with three different doping doses of the drain or drift region 12. The dashed curves HEI, HEII, HEIII show the profile characteristic of the doping concentration of the associated high-energy drain implantation, the doping dose and also the implantation energy increasing from HEI through HEII to HEIII. It holds true also for the low-voltage trench transistors according to the invention illustrated in FIG. 5 that the doping of the drain or drift region is higher than that of the body region.

A description has been given above of individual method steps for fabricating a low-voltage n-channel trench transistor according to the invention and an exemplary doping concentration characteristic of a low-voltage trench transistor of this type. It is immediately apparent to the person skilled in the art that the principle of the fabrication method according to the invention, which resides in introducing a high-energy implantation for forming the drain or drift region, applies equally to a low-voltage p-channel trench transistor.

LIST OF REFERENCE SYMBOLS

• 1, 10 substrate
• 2 buried layer
• 3, 11, 11′ epitaxial layer
• 4, 20 body region
• 5, 14 trench
• 6, 16 gate electrode
• 9, 15 gate dielectric
• 7, 13 source region
• 8, 17 source electrode contact
• 12 drift region
• C channel length
• U bottom of the trench
• n, n⁺ doping of the first conductivity type
• p doping of the second conductivity type
• O net doping with p-type epitaxy without high-energy drain implantation
• I, II, III doping concentration characteristics of a low-voltage trench transistor with high-energy drain implantation
• HeI, HeII, HeIII doping profile of the high-energy drain implantation

Claims

1-11. (canceled)

12. A method for fabricating a trench transistor, comprising:

providing an epitaxial layer disposed above a substrate, the substrate having a first conductivity type;

providing a trench and, within the trench, a gate dielectric and a gate electrode;

providing a body region of a second conductivity type adjoining the trench and a source region of the first conductivity type disposed within the body region; and

forming a drift region of the first conductivity type at the an of a junction between the substrate and the epitaxial layer using one or more high-energy implantations, a lower end of the trench disposed within said drift region, the drift region including at least a portion of a drain zone.

13. The fabrication method as claimed in claim 12, wherein providing the epitaxial layer further comprises depositing the epitaxial layer such that the epitaxial layer has a second conductivity type and subsequently forms the body region.

14. The fabrication method as claimed in claim 12, wherein providing the epitaxial layer further comprises providing the epitaxial layer having a first dopant concentration and subsequently forming the body region using the epitaxial layer, the body region having a second dopant concentration that is greater than the first dopant concentration.

15. The fabrication method as claimed in claim 12, wherein the steps of forming the drift region and providing the body region occur prior to the step of providing the trench.

16. The fabrication method as claimed in claim 12, wherein the step of providing the trench occurs before the steps of forming the drift region and providing the body region.

17. The fabrication method as claimed in claim 16, further comprising planarizing the gate dielectric and the gate electrode prior to the step of forming the drift region.

18. The fabrication method as claimed in claim 12, wherein forming the drift region further comprises using a high-energy implantation dose of approximately 1013 cm−1 to 5·1013 cm−2.

19. The fabrication method as claimed in claim 12, wherein the first conductivity type comprises an n-type and the second conductivity type comprises a p-type.

20. The fabrication method as claimed in claim 12, wherein a doping concentration of the drift region is greater than a doping concentration of the body region.

21. A trench transistor comprising:

a substrate having a first conductivity type;

an epitaxial layer disposed above the substrate;

a trench and, within the trench, a gate dielectric and a gate electrode;

a body region of a second conductivity type adjoining the trench, the body region having formed therein a source region of the first conductivity type; and

a drift region of the first conductivity type which forms a drain zone, the drift region disposed between the the substrate and the epitaxial layer and extending above and below a lower end of the trench, the drift region directly adjoining an underside of the body region.

22. The trench transistor as claimed in claim 21, wherein the first conductivity type comprises an n-type and the second conductivity type comprises a p-type.

23. The trench transistor as claimed in claim 22, wherein a doping concentration of the drift region is greater than a doping concentration of the body region.

24. The trench transistor of as claimed in claim 21, wherein at least a portion of the epitaxial layer forms the body region.

25. A method for fabricating a trench transistor, comprising:

providing an epitaxial layer disposed above a substrate, the substrate having a first conductivity type;

providing a trench configured to contain, at least in part, a gate dielectric and a gate electrode;

providing a source region of the first conductivity type within the epitaxial layer, the source region disposed adjacent the trench; and

forming a drift region of the first conductivity type using at least one implantation, such that the drift region is disposed directly above the substrate, the drift region extending above and below a lower end of the trench, the drift region including at least a portion of a drain zone.

26. The fabrication method as claimed in claim 25, wherein providing the epitaxial layer further comprises depositing the epitaxial layer such that the epitaxial layer has a second conductivity type and subsequently forms a body region, and wherein the drift region is disposed between the body region and the substrate.

27. The fabrication method as claimed in claim 25, wherein providing the epitaxial layer further comprises providing the epitaxial layer having a first dopant concentration and subsequently forming a body region using the epitaxial layer, the body region having a second dopant concentration that is greater than the first dopant concentration.

28. The fabrication method as claimed in claim 25, wherein the steps of forming the drift region and providing the source region occur prior to the step of providing the trench.

29. The fabrication method as claimed in claim 25, wherein the step of providing the trench occurs before the steps of forming the drift region and providing the source region.

30. The fabrication method as claimed in claim 29, further comprising planarizing the gate dielectric and the gate electrode prior to the step of forming the drift region.

31. The fabrication method as claimed in claim 25, wherein forming the drift region further comprises using an implantation dose of approximately 1013 cm−2 to 5·1013 cm−2.