Abstract: In an embodiment, a method includes: obtaining one or more radar measurement frames, each one of the one or more radar measurement frames including respective data samples acquired by a radar sensor monitoring a scene; for each one of the one or more radar measurement frames, determining a respective 2-D angular intensity map of the scene based on the respective radar measurement frame; and performing a people counting operation based on the one or more 2-D angular intensity maps determined for the one or more radar measurement frames to determine a people count for the scene.

Abstract: In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.

Abstract: A method for monitoring an RF receiver includes generating of a digital test signal based on a signal, wherein the digital test signal includes a stream of digital test samples having a digital test sample; generating a monitoring signal based on the digital test signal; and coupling of the monitoring signal into a receiver path. The monitoring signal is processed in the receiver path to generate a processed monitoring signal and a stream of digital monitoring samples representing the processed monitoring signal. Information is determined indicating at least one property related to the receiver path based on a processing of a set of digital monitoring samples of the stream of digital monitoring samples. The set of digital monitoring samples includes a digital monitoring sample. The method further includes controlling the RF receiver such that the digital monitoring sample is generated a predetermined time duration after generating the digital test sample.

Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.

Abstract: A circuit includes a power transistor having a main current path between a first supply node and an output pin for connecting a load. A resistance formed by a chip metallization is arranged between the main current path of the power transistor and the output pin. The circuit includes a current measuring circuit coupled to the power transistor and including a sense transistor coupled to the power transistor. The current measuring circuit delivers a measurement current representing a load current flowing through the power transistor. An amplifier circuit generates an amplifier output signal representing the voltage across the resistance, and a control circuit outputs a signal representing the measurement current in a first mode and a signal dependent on the amplifier output signal in a second mode.

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

Abstract: This disclosure describes circuits and techniques for determining inductance on an electrical line. In some examples, a method comprises charging a capacitor in time steps to a voltage level; counting a number of the time steps to the voltage level, wherein the number of the time steps defines a coarse measurement inductance of the electrical line; measuring a charging rate associated with charging the capacitor within a measurement window that is defined at the voltage level, wherein the charging rate associated with charging the capacitor within the measurement window defines a fine measurement of the inductance of the electrical line; and outputting an indication of the number of time steps and an indication of the charging rate associated with charging the capacitor within the measurement window.

Abstract: A carrier for a leadless package is disclosed. In one example, the carrier comprises a component mounting structure for mounting an electronic component thereon, and a plurality of leads arranged around at least part of the component mounting structure, wherein corner leads of said leads are located closer to at least one corner of said component mounting structure than intermediate leads of said leads located farther away from said at least one corner than said corner leads, wherein said corner leads have a larger width along a respective edge of the component mounting structure compared with a smaller width of said intermediate leads, and wherein at least said corner leads comprise a lead tip inspection feature.

Abstract: A method of manufacturing a package includes forming an adhesion promoter on at least part of an electronic component. The adhesion promoter is a morphological adhesion promoter including a morphological structure having a plurality of openings. The method further includes at least partially encapsulating the electronic component with an inorganic encapsulant with the adhesion promoter in between. The adhesion promoter enhances adhesion between at least part of the electronic component and the encapsulant.

Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

Abstract: A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network including a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.

Abstract: An apparatus for testing semiconductor devices is disclosed. In one example, the apparatus includes a rolling contactor comprising a first cylindrical rotatable holder, a plurality of test pin sets, each one of the test pin sets being connected to the cylindrical rotatable holder. Each one of the test pin sets comprises a plurality of test pins, and a substrate configured to support a plurality of semiconductor devices. The semiconductor devices comprising one or more contact elements on a main surface thereof remote from the substrate, wherein the first cylindrical rotatable holder and the substrate are arranged relative to each other so that due to a rotating movement of the first cylindrical rotatable holder the test pins of the test pin sets are successively contacted with the contact elements of the semiconductor devices.

Abstract: A printed circuit board and method of manufacturing a printed circuit board are disclosed. In one example, the method comprises embedding an electronic component in a laminate, and protecting the electronic component against electrostatic discharge during at least part of the manufacturing process by an electrically conductive electrostatic discharge protection structure integrated in the laminate and connected to the electronic component.

Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.

Abstract: Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.

Abstract: A method of manufacturing a chip structure is provided. The method includes attaching a chip to a chip carrier using a chip attach layer, wherein the chip attach layer comprises a metal having a first melting point. The chip comprises a solder layer and the chip carrier comprises a further solder layer, the solder layer and/or the further solder layer comprising a respective solder material having a second melting point lower than the first melting point. An intermetallic phase is formed between the solder material and metal of the chip attach layer by melting the solder material having the second melting point.

Abstract: An exemplary embodiment of a sensor system includes a magnet system which is designed to generate a magnetic field. Furthermore, the sensor system includes a first magnetic field sensor which is movable in a first direction relative to the magnet system and has a first distance from the magnet system in a second direction perpendicular to the first direction. The sensor system also includes a second magnetic field sensor which is movable in the first direction relative to the magnet system and has a second distance from the magnet system in the second direction, the second distance being greater than the first distance.

Abstract: A method comprises applying a driver voltage to an electrostatic comb drive of an MEMS apparatus and overlaying the driver voltage with a periodic voltage signal. The method further comprises determining a torsion angle of a mirror body of the MEMS apparatus based on the periodic voltage signal.

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

Abstract: A torque measurement system includes a first rotatable carrier structure and a second rotatable carrier structure mechanically coupled to a shaft; a first metamaterial track coupled to and configured to co-rotate with the first rotatable carrier structure; a second metamaterial track coupled to and configured to co-rotate with the second rotatable carrier structure; and a low-friction material arranged between the first and the second rotatable carrier structures. The first and the second metamaterial tracks are spaced apart by a predetermined distance and are mutually coupled to each other by a torque-dependent coupling. Responsive to a torque applied to the shaft, the first metamaterial track is configured to undergo a rotational shift relative to the second metamaterial track. The low-friction material provides a low-friction rotational shift between the first rotatable carrier structure and the second rotatable carrier structure such that the predetermined distance is constant during the rotational shift.