Semiconductor device
A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.
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This application is based upon, claims the benefit of priority of, and incorporates by reference the contents of Japanese Patent Application No. 2002-367067 filed Dec. 18, 2002 and Japanese Patent Application No. 2003-348865 filed Oct. 7, 2003.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly, to a horizontal MOS transistor.
2. Background of the Invention
A semiconductor device such as that disclosed in JP-A-2001-274398 has a structure as shown in
With such a structure, an electric current passage can be extended in a depth direction in a trench gate, and an ON resistance can be reduced.
However, taking measures against a surge into account, there is the following problem to be solved. A surge penetrating from the drain N+ region 103 flows up to a deep portion of the N− silicon substrate 100, and penetrates into the base P region 101 from a corner portion of the base P region 101 where electric fields tend to concentrate. Then, the surge flows in a vertical direction in the base P region 101 to reach the ground from the source electrode. Therefore, since a resistance in the vertical direction of the base P region 101 acts as a base parasitic resistance to cause a parasitic bipolar transistor, which is constituted by the source N+ region 102, the base P region 101, and the N− layer (100), to be easily turned ON, the semiconductor device is susceptible to the surge.
SUMMARY OF THE INVENTIONThe present invention has been devised in view of such a background, and it is an object of the invention to provide a semiconductor device, which realizes reduction of an ON resistance and is resistant to a surge, and a method of manufacturing the same.
A first aspect of the invention is a semiconductor device that is provided with a trench. The trench is formed from a principal surface of a semiconductor substrate to penetrate a base region in a direction toward a drain region from a source region as a planar structure thereof. Thus, by adopting a trench gate structure, an electric current passage can be extended in a depth direction, and the ON resistance can be reduced. In addition, the semiconductor device is also provided with a well region. The well region includes the drain region in a surface layer portion on the principal surface. The well region is formed deeper than the drain region and with a higher concentration than the semiconductor substrate in a region in contact with the base region, and has a first conductivity type. Thus, a surge having penetrated from the drain region penetrates into the well region and flows on a surface side of the base region through the well region having a low resistance to be absorbed in the ground by a source electrode. Therefore, since the surge never flows in a vertical direction in the base region, a parasitic resistance of the base region decreases, and the semiconductor device becomes resistant to the surge.
A second aspect of the invention is a semiconductor device which is provided with a trench. The trench is formed from a principal surface of a semiconductor substrate to penetrate a base region in a direction toward a collector region from an emitter region as a planar structure thereof. Thus, by adopting a trench gate structure, an electric current passage can be extended in a depth direction, and the ON resistance can be reduced. In addition, the semiconductor device is also provided with a well region. In a surface layer portion on the principal surface, this well region is formed deeper than the collector region and with a higher concentration than the semiconductor substrate in a region including the collector region and is in contact with the base region. The well region has a first conductivity type. Thus, a surge having penetrated from the collector region penetrates the well region and flows on a surface side of the base region through the well region having a low resistance to be absorbed in the ground by an emitter electrode. Therefore, since the surge never flows in a vertical direction in the base region, a parasitic resistance of the base region decreases, and the semiconductor device becomes resistant to the surge.
In a third aspect of the invention, in the semiconductor device of the first or the second aspect of the invention, at least in the surface layer portion on the principal surface in the base region, abase contact region of a second conductivity type, which is shallower and has a higher concentration than the base region, is formed between the source region or the emitter region and the drain region or the collector region. Consequently, as shown in
In a fourth aspect of the invention, in the semiconductor device in any one of the first to the third aspects of the invention, the concentration increases continuously from a bottom to a surface in the well region. Then, a surge is flown to the surface of the well region, whereby it becomes easy to flow the surge to a surface of the base region, and a path of the surge in the base region is shortened. Consequently, a parasitic base resistance can be reduced to suppress an increase in a potential of the base region, and a surge current capacity can be improved.
In a fifth aspect of the invention, in the semiconductor device in the third aspect of the invention, the base contact region is formed apart from the trench, and a gate electrode is formed on the principal surface via a gate insulating film. Then, a region operating as a channel can be formed on the principal surface of the semiconductor substrate to decrease the ON resistance.
In a sixth aspect of the invention, in the semiconductor device in any one of the first to the fifth aspects, the semiconductor device has an embedded layer of a first conductivity type, which has a higher concentration than the semiconductor substrate, in a bottom of the semiconductor substrate, and a bottom surface corner portion of the trench is made deeper than the well region and shallower than the embedded layer. Then, the vicinity of the bottom surface corner portion of the trench where electric fields tend to concentrate can be turned into a region with a low impurity concentration to prevent the concentration of electric fields and improve a withstand voltage.
In a seventh aspect of the invention, in the semiconductor device in any one of the first to the sixth aspects, a gate electrode is arranged in an opening of the source region or the emitter region on a side of the trench. Then, the semiconductor device becomes preferable for practical use.
In an eighth aspect of the invention, in the semiconductor device in any one of the first to the fifth and the seventh aspects, an SOI substrate is used, and the trench is formed to reach an embedded insulating film of the SOI substrate. Then, a trench for device separation and a trench for gate can be created simultaneously.
In a ninth aspect of the invention, in the semiconductor device in any one of the first to the fifth, the seventh, and the eighth aspects, an SOI substrate is used, and a thickness of a semiconductor layer on an embedded insulating film in the SOI substrate is made equal to a depth of the well region. Then, by reducing a film thickness of the semiconductor layer as much as possible, a depth of a trench for device separation can be reduced, and cost for etching in creating the trench by etching can be reduced.
In a tenth aspect of the invention, in the semiconductor device in any one of the first to the ninth aspects, the drain region or a collector region and the well region form an island shape, and the base region exists around the regions. Then, the semiconductor device is preferable in improving a surge current capacity.
In an eleventh aspect of the invention, in the semiconductor device in any one of the first to the ninth aspects, a source cell or an emitter cell and a drain cell or a collector cell are arranged alternately lengthwise and crosswise adjacent to each other. Then, the semiconductor device is preferable for practical use.
In a twelfth aspect of the invention, in the semiconductor device in any one of the first to the ninth aspects, at least a source contact or an emitter contact in an outermost circumference in a group of cells provided in parallel adjacent to each other are set larger in size than inner source contacts or emitter contacts. Then, the semiconductor device is preferable in improving a surge current capacity.
In a thirteenth aspect of the invention, in the semiconductor device in any one of the first to the ninth aspects, a base contact region of a second conductivity type having a higher concentration than the base region is formed in at least the surface layer portion on the principal surface in the base region in a position, where at least the source region or an emitter region in an outermost circumference in a group of cells provided in parallel adjacent to each other is planned to be arranged, instead of the source region or the emitter region. Then, the semiconductor device is preferable in improving a surge current capacity.
In a fourteenth aspect of the invention, in the semiconductor device in the thirteenth aspect, the drain region or the collector region is surrounded by the source region or the emitter region and the base contact region as a planar structure. Then, the semiconductor device is preferable in improving a surge current capacity.
In a fifteenth aspect of the invention, a method of manufacturing the semiconductor device in the fifth aspect of the invention is provided, which comprises: arranging an insulating film, in which a region where a base contact is planned to be formed is opened as a contact hole, on the principal surface after forming the base region, the source region, the drain region, the well region, and the trench, and performing ion implantation using the insulating film as a mask to form a base contact region apart from the trench in the surface layer portion on the principal surface. Thus, an impurity for forming the base contact region is prevented from diffusing to reach the trench.
In a sixteenth aspect of the invention, a method of manufacturing the semiconductor device in the fifth aspect of the invention is provided, which comprises: arranging an insulating film, in which a region where a base contact is planned to be formed is opened as a contact hole, on the principal surface after forming the base region, the emitter region, the collector region, the well region, and the trench; and performing ion implantation using the insulating film as a mask to form a base contact region apart from the trench in the surface layer portion on the principal surface. Thus, an impurity for forming the base contact region is prevented from diffusing to reach the trench.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
A first embodiment in which the present invention is embodied will be hereinafter described in accordance with the accompanying drawings.
In addition, in the respective island (the first to the third device formation island in
Concerning the CMOS transistor in the logic portion, a P well region 10 is formed for an N channel MOS in a surface layer portion of the N− silicon layer 3. The P well region 10 is formed to have an impurity concentration of about 1.0×1017/cm3. A source N+ region 11 and a drain N+ region 12 are formed apart from each other in a surface layer portion of the P well region 10. In addition, a gate electrode 13 is arranged on the P well region 10 via a gate oxide film (not shown).
As a P channel CMOS, a source P+ region 14 and a drain P+ region 15 are formed apart from each other in the surface layer portion of the N− silicon layer 3. Moreover, a gate electrode 16 is arranged on the N− silicon layer 3 via a gate oxide film (not shown).
Concerning the NPN transistor in the bipolar transistor portion, a P well region 20 is formed in the surface layer portion of the N− silicon layer 3, and an emitter N region 21 and a base P+ region 22 are formed apart from each other in a surface layer portion of the P well region 20. An emitter contact N+ region 23 is formed in the emitter N region 21. In addition, a collector N region (deep N region) 24 is formed apart from the P well region 20 in the surface layer portion of the N-silicon layer 3. The collector N region (deep N region) 24 reaches the embedded N+ layer 8. An N+ contact region 25 is formed in a surface layer portion of the collector N region (deep N region) 24. The base P+ region 22, the emitter contact N+ region 23, and the N+ contact region 25 have a high concentration (1.0×1020/cm3) and are in contact with a base electrode, an emitter electrode, and a collector electrode, respectively.
The horizontal MOS transistor in the power MOS portion will be described. Details of a Y portion in
As shown in
In
A source N+ region 31 is formed shallower than the base P region 30 in the surface layer portion of the N− silicon layer 3 (principal surface 3a of the substrate) in the base P region 30. The source N+ region 31 has a surface concentration of 1.0×1020/cm3 and a depth of 0.2 to 0.3 μm.
In the surface layer portion in the N− silicon layer 3 (principal surface 3a of the substrate), a drain N+ region 32 is formed in a position apart from the base P region 30. The drain N+ region 32 has a surface concentration of 1.0×1020/cm3 and a depth of 0.6 to 1.2 μm. In a process of forming the drain N+ region 32, ion implantation of phosphorus shares a mask with ion implantation for the emitter contact N+ region 23 (see
In the surface layer portion in the N− silicon layer 3 (principal surface 3a of the substrate), an N well region 33 is formed to be deeper than the drain N+ region 32 and to have a higher concentration than the N− silicon layer 3 in a region including the drain N+ region 32 and in contact with the base P region 30. More specifically, in the N− silicon layer 3, the N well region 33 has a concentration of about 1.0×1016/cm3 and is formed to overlap the base P region 30 with a concentration of about 1.0×1017/cm3. The N well region 33 has a depth of approximately 2 to 4 μm. In addition, in the N well region 33, a concentration increases continuously from a bottom to a surface thereof.
In the surface layer portion in the N− silicon layer 3 (principal surface 3a of the substrate), in particular, the base P region 30, a base contact P+ region 34 is formed further on the drain N+ region 32 side than the source N+ region 31. The base contact P+ region 34 is shallower and has a higher concentration than the base P region 30, and has a surface concentration of 1.0×1020/cm3 and a depth of 0.5 μm.
As shown in
As shown in
As shown in
Since a depth of the trench 35 (gate electrode 37) affects a withstand voltage, it is an important parameter in terms of withstand voltage design. In the vicinity of the trench 35, concentration of electric fields occurs in a corner portion (A1 in
As shown in
Dependency of the depth of the trench 35 upon a withstand voltage was checked by simulation. As a result, it was found that a device having a withstand voltage of 41 volts at a depth of a trench of 3 μm had an improved withstand voltage of 65 volts at a depth of the trench of 5 μm.
Next, operations of the horizontal power MOS transistor will be described.
At the time when the device is OFF (drain potential: 0.2 volts, gate potential: 0 volt, source potential: 0 volt), since electrons do not reach the base P region 30 from the source N+ region 31, an electric current does not flow.
At the time when the device is ON (drain potential: 0.2 volts, gate potential: 7 volts, source potential: 0 volt), an inversion layer is formed in a portion which is in contact with the gate oxide films 36 and 38 in the base P region 30. Then, electrons reach the surface of the trench 35 and the inversion layer on the upper surface of the substrate from the source N+ region 31. Next, the electrons reach the N well region 33 from the surface of the trench 35 and the inversion layer on the upper surface of the substrate. At this point, since the depth of the trench 35 is 4 to 6 μm and the depth of the N well region 33 is 2 to 4 μm, the electrons reach the depth of 2 to 4 μm in the N well region 33.
Next, the electrons reach the drain N+ region 32 from the N well region 33. In this case, since the depth of the N+ region 32 is 0.6 to 1.2 μm, the electrons also exist in a deep portion even as the electrons approach the drain N+ region 32.
In this way, a path of the electric current is formed deep into the inside of the silicon layer 3 (or portion distant from the surface). Therefore, the ON resistance can be reduced. More specifically, as a simulation result, it was found that the above configuration achieved an ON resistance was 63.4 mΩ·mm2, which was about half compared with a conventional device having only a surface gate without using a trench gate.
Next, operations in the case in which an electrostatic surge has penetrated into the semiconductor device will be described with reference to
In
In particular, the base contact P+ region 34 is formed between the source N+ region 31 and the drain N+ region 32 for reducing a parasitic base resistance. Detailed description will be made with reference to
As described above, in this embodiment, the horizontal power MOS transistor with a high surge current capacity can be provided. In particular, in the simulation result, endurance of an electrostatic test (see
(A) As shown in
(B) In at least the surface layer portion on the principal surface 3a in the base P region 30, the P type base contact region having a high concentration (the base contact P+ region 34) is formed shallower than the base P region 30 between the source N+ region 31 and the drain N+ region 32. Consequently, as shown in
(C) A concentration increases continuously from the bottom to the surface in the N well region 33. Thus, a surge is flown to the surface of the N well region 33, whereby it becomes easy to flow the surge to the surface of the base P region 30, and a path of the surge in the base P region 30 is shortened. Consequently, a parasitic base resistance can be reduced to suppress an increase in a potential of the base P region 30, and a surge current capacity can be improved.
(D) The base contact region (base contact P+ region 34) is formed apart from the trench 35, and the gate electrode 39 is formed on the principal surface 3a via the gate oxide film (gate insulating film) 38. Thus, a region operating as a channel on the principal surface 3a of the substrate can be formed to reduce an ON resistance.
(E) In the bottom of the N− silicon layer (semiconductor substrate) 3, the transistor has the N+ type embedded layer (embedded N+ layer 9) having a concentration higher than that of the N− silicon layer 3, and the bottom corner portion of the trench 35 is made deeper than the N well region 33 and shallower than the embedded N+ layer 9. Thus, the vicinity of the bottom corner portion of the trench 35 where electric fields tend to concentrate is turned into a region with a low impurity concentration, whereby the concentration of electric fields can be prevented, and a withstand voltage can be improved.
In
In this way, by adopting the structure of
In addition, in
Next, a second embodiment will be described focusing on differences from the first embodiment.
As compared with the first embodiment, in this embodiment, a source N+ region 50 also shares a mask with the emitter contact N+ region 23 of the bipolar transistor portion (see
With such a structure, an electric current can be flown to the deeper portion of the trench 35 than in the first embodiment.
Third EmbodimentNext, a third embodiment will be described by emphasizing differences with the first embodiment.
In the case of the first embodiment shown in
Thus, this embodiment copes with the problem as described below.
In
Next, a fourth embodiment will be described by emphasizing differences with the first embodiment.
In the case in which the MOS transistor shown in FIGS. 2 to 5 is manufactured, formation of the base contact P+ region 34 is usually performed as follows. First, as shown in
Therefore, this embodiment copes with the problem as described below.
First, as shown in
According to this process, diffusion of P+ can be suppressed.
As described above, in this embodiment, a method of manufacturing a semiconductor device, in which the base contact P+ region 34 is formed apart from the trench 35 as shown in
Next, a fifth embodiment will be described by emphasizing differences with the first embodiment.
The embedded N+ layer 8 among the embedded N+ layers 7, 8, and 9 in
In addition, in this case, the thickness of the silicon film on the insulating film 2 only has to sufficient for allowing the depth of the N well region 33 to be secured. Thus, the thickness can be as small as 2 to 4 μm. Further, because the trench for device separation 4 (see
Next, a sixth embodiment will be described by emphasizing differences with the first embodiment.
In the plan view of
In this layout, since the drain N+ regions 32 and the N well regions 33 are surrounded by the base P regions 30, an electric current path can be widened. Consequently, a surge current capacity can be improved at the time of surge penetration. In addition, in this layout, wider base contact P+ regions 34 can be achieved. Therefore, concentration of electric currents on the base contact P+ regions 34 can be prevented at the time of surge penetration to improve a surge current capacity.
In addition, in this embodiment, as shown in
Next, a seventh embodiment will be described by emphasizing differences with the first embodiment.
In this embodiment, as shown in
This embodiment will be hereinafter described in detail.
In this embodiment, a layout is adopted in which the source cells 42 and the drain cells 43 are arranged alternately in the plan view of
The base P region 30 is formed in the surface layer portion in the source cell 42. In
In the drain cell 43 of
In addition, in
A mechanism of brake down in the outermost circumference of the group of cells will be described with reference to
The end of the base P region 30′ is formed in a semicircular shape in the outermost circumference of the group of cells, and a PN junction portion between the base P region 30′ and the N well region 33′ has a radius of curvature R11. In the PN junction portion with the radius of curvature R11, electric fields tend to concentrate, and a hole is easily generated due to impact ionization. The hole turns into a base electric current of a parasitic bipolar to cause a parasitic bipolar operation, and electric currents concentrate on the external circumferential portion to cause destruction.
On the other hand, in
In this way, the external circumferential portion is constituted only by the source cell 42 as shown in
In addition, an electrode size in
The drain electrode 41 is formed on the surface of the drain N+ region 32 and has an area in one cell of about 1 μm2. However, the source electrode 40 is arranged on the source N+ region 31 and the base contact P+ region 34 and has an area in one cell of about 2 μm2. Here, an area of a part of the source electrode 40 existing on the source N+ region 31 is about 1 μm2, and a part existing on the base contact P+ region 34 is about 1 μm2.
Then, at the time when the device is ON (drain potential: 0.2 volts, gate potential: 7 volts, source potential: 0 volt), an electric current flows from the source N+ regions 31 to the source electrodes 40. At this point, an area of a portion used as an electrode is 1 μm2, which is equal to the area of the drain electrode 41. Therefore, deviation of an electric current is reduced, and the electric current flows to each cell uniformly.
In the case in which an electrostatic surge penetrates into the device, since the device operates as a diode, an electric current flows from the base contact P+ region 34 to the source electrode 40 (see
Next, an eighth embodiment will be described by emphasizing differences with the first embodiment.
This embodiment has a structure in which cells in an outermost circumference in a group of cells are different from the other cells. More particularly, at least a source contact 44 in the outermost circumference in the group of cells, in which cells are provided in parallel adjacent to each other, is made larger than an inner source contact 45 (a source contact is large only in the outermost circumference of the group of cells).
In addition, a base contact P+ region 46 is formed in a position where at least the source N+ region 31 in the outermost circumference is planned to be arranged in the group of cells in which cells are provided in parallel adjacent to each other, instead of the source N+ region 31. The base contact P+ region 46 is formed at least in the surface layer portion on the principal surface 3a in the base P region 30 with a higher concentration than the base P region 30 (more specifically, the base contact P+ region 46 is shallower than the base P region 30). More particularly, the source N+ region 31 does not exist in the cells in the outermost circumference in the group of cells, and the P+ region 46 is formed instead of the source n+region 31. More particularly, as shown in
With this structure, the following effects are realized compared with the structure shown in
In the stripe structure of
On the other hand, in
Note that, if the cells in the vicinity of the outermost circumference in the group of cells are formed with the same structure as those in the outermost circumference, EST endurance is further improved.
Ninth EmbodimentNext, a ninth embodiment will be described by emphasizing differences with the eighth embodiment.
As a planar structure, the drain N+ region 32 is surrounded by the source N+ region 31 and the base contact P+ region 47. More particularly, the P+ region 46 in the outermost circumference in the eighth embodiment (
In this case, a diode structure is obtained in which the drain N+ region 32 is a cathode and the P+ region 47 is an anode. This diode can be used as a protective diode by setting a withstand voltage (breakdown voltage) of the diode lower than a withstand voltage (breakdown voltage) of the transistor in the inside. In order to set the withstand voltage (breakdown voltage) low, more specifically, for example, a distance X2 between the drain N+ region 32 and the P+ region 47 in the outermost circumference is set smaller than a distance X1 between the drain N+ region 32 and the base contact P+ region 34 inside the transistor. Thus, in the case in which a surge penetrates into the drain N+ region 32, the following situation occurs. The surge is about to penetrate into the base contact P+ region 34 inside the transistor and the P+ region 47 in the external circumferential portion through the N well region 33. However, since a withstand voltage (breakdown voltage) between the P+ region 47 in the external circumferential portion and the drain N+ region 32 is lower than a withstand voltage between the base contact P+ region 34 inside the transistor and the drain N+ region 32, the surge flows to the external circumferential portion, and the transistor in the inside is protected. In this way, a surge current capacity can be improved.
Tenth EmbodimentNext, a tenth embodiment will be described by emphasizing differences with the first to the ninth embodiments.
In the first to the ninth embodiments, the invention is applied to a MOSFET. However, in this embodiment, the invention is applied to an IGBT (insulating gate type bipolar transistor). More particularly, a P+ region 80 is formed instead of the drain N+ region 32 in
A structure in the case in which the invention is applied to the IGBT can be implemented in the same manner as the case of the MOSFET described above (in the same manner as the first to the ninth embodiment).
The description of the invention is merely exemplary in nature and, thus, variations that do not depart from the gist of the invention are intended to be within the scope of the invention. Such variations are not to be regarded as a departure from the spirit and scope of the invention.
Claims
1-15. (canceled)
16. A semiconductor device comprising:
- an emitter region of a first conductivity type;
- a base region of a second conductivity type formed in a surface layer portion on a principal surface in a semiconductor substrate of a first conductivity type, the emitter region of the first conductivity type being formed to be shallower than the base region in the surface layer portion on the principal surface in the base region;
- a collector region of the second conductivity type formed in a position apart from the base region in the surface layer portion on the principal surface;
- a well region of the first conductivity type disposed in the surface layer portion on the principal surface, the well region is formed to be deeper than the collector region and to have a higher concentration than the semiconductor substrate in a region including the collector region and to be in contact with the base region;
- a trench formed in the principal surface of the semiconductor substrate to penetrate the base region in a direction toward the collector region from the emitter region as a planar structure thereof;
- a gate electrode which is formed via a gate insulating film in the inside of the trench;
- an emitter electrode which is electrically connected to the emitter region; and
- a collector electrode which is electrically connected to the collector region.
17. A method of manufacturing the semiconductor device of claim 16, the method comprising:
- arranging an insulating film in which a region where a base contact is to be formed is opened as a contact hole on the principal surface after forming the base region, the emitter region, the collector region, the well region, and the trench; and
- performing ion implantation using the insulating film as a mask to form a base contact region apart from the trench in the surface layer portion on the principal surface.
18. A semiconductor device according to claim 16, wherein, at least in the surface layer portion on the principal surface in the base region, a base contact region of the second conductivity type is shallower and has a higher concentration than the base region and is formed between the emitter region and the collector region.
19. A semiconductor device according to claim 16, wherein the concentration of the well region increases continuously from a bottom to a surface.
20. A semiconductor device according claim 16, further comprising another gate electrode arranged in an opening of the emitter region on a side of the trench.
21. A semiconductor device according to claim 16, wherein the collector region and the well region form an island shape, and the base region exists around the collector and the well regions.
22. A semiconductor device according to claim 16, further comprising an emitter cell and a collector cell arranged alternately lengthwise and crosswise adjacent to each other.
23. A semiconductor device according to claim 16, further comprising at least an emitter contact in an outermost circumference in a group of cells provided in parallel adjacent to each other and that is set larger in size than inner emitter contacts.
24. A semiconductor device according to claim 16, further comprising a base contact region of a second conductivity type having a higher concentration than the base region formed in at least the surface layer portion on the principal surface in the base region in a position, where at least the emitter region in an outermost circumference in a group of cells provided in parallel adjacent to each other is to be arranged.
25. A semiconductor device according to claim 24, wherein the collector region is surrounded by the emitter region and the base contact region as a planar structure.
Type: Application
Filed: Jun 21, 2005
Publication Date: Oct 20, 2005
Applicant:
Inventors: Naohiro Suzuki (Anjo-city), Jun Sakakibara (Anjo-city), Yoshitaka Noda (Bisai-city), Hitoshi Yamaguchi (Nisshin-city)
Application Number: 11/156,451