Low noise audio amplifier

Abstract

An amplifier circuit performs audio signal processing and other signal processing by using a noise reduction feedback network. The noise reduction feedback network turns on automatically when output signals are in or near voltage saturation state. The network provides feedback signals to the input terminals of the amplifier's control stage and modulates the control signals. It prevents audio frequency noise associated with “clipping”.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to U.S. provisional patent application Ser. No. 60/620,149, filed on Oct. 18, 2004, which is hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to audio signal processing, and in particular, relates to a system that includes a Class D amplifier for audio signal amplification and other audio signal processing.

BACKGROUND INFORMATION

Class-D audio amplifiers are often used for audio amplification because of their power efficiency. Typically, the Class D audio amplifier is operated in the switch mode with minimized internal power consumption. It produces a rectangular wave at the output stage that is filtered before delivered to a load. The filtered signal wave is an amplified version of the input signal wave. Class D audio amplifiers are usually used for high power applications. For low power applications, Class A/B amplifiers are still popular.

When the input audio signal exceeds the audio amplifier's linear range, the output of the amplifier saturates. Oscillations at the audible band are often observed when the amplifier enters the saturation condition and exits the saturation condition, as indicated in FIG. 6. This may result in the “clipping” of audible noises. This problem is more severe in the class D audio amplifier because the switching power supply can skip switching cycles due to the minimum on and off time constraints. If the power supply skips sufficient cycles, the effective operation frequency may enter the audible frequency range and induce unexpected audible noises.

There are several known methods to resolve the problem. The first method is to limit the amplitude of the input signal with a clamping circuit. However, without information on the audio source's output impedance, this may not be practical and can degrade the audio signal quality. The second method is to add an automatic gain control (AGC) pre-amplifier before the input of the class-D audio amplifier. This AGC pre-amplifier limits the input signal amplitude to prevent the output saturation, but the implementation is rather complex and adds a significant cost. The limitation may get more severe for low frequency audio signals. The third method is to add a high-pass filter to limit the minimum audio frequency passing into the class-D amplifier, but may not solve the problem completely.

Accordingly, more improvements are needed to reduce audio noise near saturation in the class D audio amplifier.

SUMMARY

The following embodiments and aspects are illustrated in conjunction with systems, circuits, and methods that are meant to be exemplary and illustrative. In various embodiments, the above problem has been reduced or eliminated, while other embodiments are directed to other improvements.

A method introduces a noise reduction feedback network. The noise reduction feedback network is coupled to an output stage and a control stage of an audio amplifier. It includes a detect circuit and a modulation circuit. The detect circuit is coupled to the output stage to monitor output voltages, detect output voltages near saturation states, and produce a control signal or multiple control signals to the modulation circuit. Once output voltages are near saturation state, the modulation circuit produces adjustable currents to the control stage to modulate output signal(s) and remove audible oscillations near saturation.

In a non-limiting embodiment, the detect circuit may include two back-to-back transistors or two back-to-back “Zener” diodes being coupled to the output stage. The two transistors are activated once the output voltages are in the near saturation states. Adjustable signals are produced by the modulation circuit according to the output voltages when two transistors are activated. These adjustable signals feed back to the control stage. The sinusoidal output waveforms become more “curved” rather than being clipped in near saturation region.

In another non-limiting embodiment, the detect circuit may include a transistor coupled between a supply voltage, Vcc, and the output stage, and a second transistor coupled between the ground and the output stage. Both transistors are activated as long as the output voltage is not in a near saturation state. The first transistor becomes deactivated once the output voltage is near the Vcc region and the second transistor becomes deactivated once the output voltage is near the ground voltage region. The first transistor is also coupled to a third transistor in the current circuit. These two transistors are such coupled that the third transistor is only activated once the first transistor is deactivated and becomes deactivated once the first transistor is activated. The second transistor is also coupled to a fourth transistor in the current circuit. These two transistors are such coupled that the fourth transistor is only activated once the second transistor is deactivated and becomes deactivated once the second transistor is activated. If the output voltage is near saturation state, either the third transistor or the fourth transistor in the current circuit produces an adjustable current to the control stage to modulate the output signals.

BRIEF DESCRIPTION OF DRAWINGS

The following figures illustrate embodiments of the invention. These figures and embodiments provide examples of the invention and they are non-limiting and non-exhaustive.

FIG. 1 is a circuit schematic showing embodiments of a system having a Class D amplifier and other components that are useable for audio signal amplification and other audio signal processing.

FIG. 2 is an example of the invention in a bridge tied load (BTL) Class D amplifier.

FIG. 3 shows output waveforms with and without the invention in the BTL Class D amplifier.

FIG. 4 is a circuit block diagram showing embodiments of a system having an audio amplifier and other components that are useable for audio signal amplification and other audio signal processing.

FIG. 5 is another example of a noise reduction feedback network.

FIG. 6 shows a waveform with “clipping” audible noise in an amplifier without the present invention.

DETAILED DESCRIPTION

Embodiments of a system and method that uses an audio amplifier and accompanying circuitry to achieve low noise audio signal amplification and other audio signal processes are described in detail herein. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc.

The present invention relates to circuits and methods of producing low noise amplified audio signals. Proposed circuits in an audio amplifier can monitor output signals, detect output signals near saturation state, and produce an adjustable current to a control stage of the amplifier to modulate output signals and remove oscillation near saturation.

FIG. 1 is an embodiment of a system according to the invention. The system comprises a control stage, A, an output stage, O, and a noise reduction feedback network, Y.

An input signal, Vin, is coupled to an input node, X1, through a capacitor, Cin1, and a resistor, Rin1. Another input node, X2, is coupled to ground through a resistor, Rin2, and a capacitor, Cin2. The nodes, X1 and X2, are coupled together by a capacitor, C2. The signals at the node, X1, comprise three components: AC portions of Vin, a feedback signal from the node, S1, and a feedback signal from the upper portion of a noise reduction feedback network, Y. The signals at the node, X2, comprise three components: a portion of signal from X1 coupled through C2, a feedback signal from the node, S2, and a feedback signal from the lower portion of the noise reduction feedback network, Y.

The control stage A includes 4 transistors, M1, M2, M3, and M4, that serve as power output switching devices. M1 and M2 drive output switching node, S1; while M3 and M4 drive output switching node, S2. In the upper half of the control stage A, M2's source terminal is coupled to ground and M1's drain terminal is coupled to a power supply, Vcc. M2's drain terminal and M1's source terminal are both coupled to the switching node S1. The node S1 is coupled to the input node, X1, through a resistor, Rfb1. In the lower half of the control stage A, M4's source terminal is coupled to ground and M3's drain terminal is coupled to the power supply, Vcc. M4's drain terminal and M3's source terminal are both coupled to the switching node S2. The node S2 is coupled to the input node, X2, through a resistor, Rfb2.

The noise reduction feedback network comprises adjustable current sources (I₁ and I₂), and a control circuit triggered by the output signal difference between V+ and V−, Vd. The control circuit is in an “OFF” state unless Vd exceeds a preset voltage level. The adjustable current sources are controlled by the control circuit. When current sources are turned on by the control circuit, extra current flows to the input nodes, X1, and X2. This extra current sets the minimum switching frequencies of two comparators, CMP1 and CMP2, in the control stage A. The input node, X1, is a negative summing node for the comparator, CMP1, and it is a positive summing node for the comparator, CMP2. The input node, X2, is a positive summing node for the comparator, CMP1, and it is a negative summing node for the comparator, CMP2. The output signal of CMP1 provides an input signal of a logic gate driver, LDR1. An output of LDR1, LDR11, drives the gate of the transistor, M1. Another output of LDR1, LDR12, drives the gate of the transistor, M2. The output signal of CMP2 provides an input signal of a logic gate driver, LDR2. An output of LDR2, LDR21, drives the gate of the transistor, M3. Another output of LDR2, LDR22, drives the gate of the transistor, M4.

In output stage, O, a rectangular waveform at the node S1 is filtered by an inductor, LL1, and a capacitor, Cout1, which is coupled to ground, and then delivered to an output node, V+. A rectangular waveform at the node S2 is filtered by an inductor, LL2, and a capacitor, Cout2, which is coupled to ground, and then delivered to an output node, V−. The output stage O is used to drive a load, such as a loudspeaker, SP. A capacitor, C3, is connected in parallel with SP and coupled between V+ and V−.

An example of one embodiment of the present invention used in a bridge tied load (BTL) Class D amplifier is shown FIG. 2. The system comprises a class D amplifier circuit AA, an output stage, OO, and a noise reduction feedback network, YY.

An input signal is coupled to a node XX1 through a capacitor, C6, and a resistor R3. Ground is coupled to a node XX2 through a capacitor, C28, and a resistor R6. The capacitor, C6, is introduced to block DC components of input signal. XX1 and XX2, are coupled by a capacitor, C12. The signal at a node SW1 is fed back to XX1 through a resistor, R10, a grounded capacitor, C17, and a resistor, R11. The signal at a node SW2 is fed back to XX2 through a resistor, R18, connected to a grounded capacitor, C16, and through a resistor, R19.

The rectangular waveform at SW1 is filtered by an inductor, L1, and a capacitor, C7, and then delivered to an output node OUT 1+. The rectangular waveform at SW2 is filtered by an inductor, L2, and a capacitor, C22, and then delivered to an output node OUT 1−. The stage OO further includes a loudspeaker, SP1:A, and a capacitor, C9, connected in parallel with SP1:A and coupled between OUT 1+ and OUT 1−. C9 filters high frequency noise between nodes OUT1+ and OUT1−.

The noise reduction feedback network YY connects the output node, OUT1+ and OUT1−, and the input nodes, XX1 and XX2. A node, T1, is connected with OUT1+ through a resistor, R30. A node, T2, is connected with OUT1− through a resistor, R31. The node T1 is connected with the node T2 through a resistor R29. The combination of R29, R30, and R31 helps to define adjustable currents of the circuit YY in the discussion below.

The node T1 is also connected to the node T2 through a resistor, R12, two back-to-back transistors Q11 and Q12, and a resistor, R15. In the upper half of the circuit YY, the emitters and collectors of transistors Q11 and Q12 are all connected. The base of the transistor Q11 is connected to the bases of a transistor Q7, and a transistor Q8. The emitters of the transistor Q7 and the transistor Q8 are connected and further connected to the node T1 through a resistor R36. The collector of the transistor Q7 is connected to the node X1 through a diode, D22, and a resistor R22; and the collector of the transistor Q8 is connected to the node X1 through a diode, D21, and the resistor R22. In the lower half of the circuit YY, the base of the transistor Q12 is connected to the bases of a transistor Q9, and a transistor Q10. The emitters of the transistor Q7 and the transistor Q8 are connected and further connected to the node T2 through a resistor R37. The collector of the transistor Q9 is connected to the node XX2 through a diode, D23, and a resistor R24; and the collector of the transistor Q10 is connected to the node X2 through a diode, D24, and the resistor R24.

The back-to-back transistors, Q11 and Q12, have a minimum turn-on voltage, V1. The transistors, Q7, Q8, Q9, and Q10, typically have a turn-on voltage V2. In the conditions, the voltage difference, Vd, between the node OUT1+ and the node OUT1− exceeds V1. The transistors, Q11 and Q12 are turned on. Once |Vd| exceeds V1+2V2, either Q7 or Q8 is turned on in the upper half of circuit YY. The current feeds back to the node XX1 through either D22 or D21 and the resistor, R22. The extra current increases the voltage switching frequency at the node XX1 and defines a minimum switching frequency for the top comparator in the upper half of YY. The increased minimum frequency produces a more “curved” sinusoidal waveform in the near “clipping” range. This helps to eliminate the audio noises when output sinusoidal waves enter and exit the voltage “clipping” range. A similar analysis applies to the lower half of circuit YY. Once |Vd| exceeds V1+2V2, either Q9 or Q10 is turned on in the lower half of circuit YY. The current feeds back to the node XX2 through either D23 or D24 and the resistor, R24. The extra current increases the voltage switching frequency at the node XX2 and defines the minimum switching frequency for the lower comparator in the lower half of YY.

FIG. 3 illustrates output waveforms in the BTL Class D amplifier with and without the present invention. The BTL circuit without the noise reduction feedback network produces low frequency oscillation that may be in the audible frequency range; however; the circuit with the network produces clean output voltages without any low frequency oscillations.

The noise reduction feedback network is not limited to the example given above. It can be applied to any class D audio amplifier and other audio amplifiers. FIG. 4 provides schematic showing a system that comprises an audio input, a control stage, an output stage, and a noise reduction network that receives the feedback signals from the output stage. The noise reduction network modulates the control stage to eliminate the audible oscillation at the output stage when the output is near saturation.

Another example of embodiments of the invention is illustrated in FIG. 5. Vout+ and Vout− are two input nodes of a noise reduction feedback network while FB1 and FB2 are two output nodes of the noise reduction network in FIG. 5(a). FIGS. 5(b) and 5(c) are detailed schematics showing embodiments of the circuit. In FIG. 5(b), Vout+ is connected to the base of a transistor, Q3, through a resistor, R13, and the base of a transistor, Q4, through a resistor, R14. The emitter of the transistor, Q3, is coupled to a power source, Vcc, and the emitter of the transistor, Q4, is coupled to the ground. The base of a transistor, Q1, is connected to the collector of the transistor, Q3, and they are coupled to the ground through a resistor, R5. The emitter of the transistor, Q1, is coupled to the power source, Vcc, through a resistor, R1; while the collector of Q1 is connected to a node FB1 through a resistor, R2. The base of a transistor, Q2, is connected to the collector of the transistor, Q4, and they are coupled to the power source, Vcc, through a resistor, R6. The emitter of the transistor, Q2, is coupled to the ground through a resistor, R4; while the collector of Q2 is connected to the node FB1 through a resistor, R3. In FIG. 5(c), Vout− is connected to the base of a transistor, Q7, through a resistor, R15, and the base of a transistor, Q8, through a resistor, R16. The emitter of the transistor, Q7, is coupled to the power source, Vcc, and the emitter of the transistor, Q8, is coupled to the ground. The base of a transistor, Q5, is connected to the collector of the transistor, Q7, and they are coupled to the ground through a resistor, R11. The emitter of the transistor, Q5, is coupled to the power source, Vcc, through a transistor, R7; while the collector of Q5 is connected to a node FB2 through a resistor, R8. The base of a transistor, Q6, is connected to the collector of the transistor, Q8, and they are coupled to the power source, Vcc, through a resistor, R12. The emitter of the transistor, Q6, is coupled to the ground through a resistor, R10; while the collector of Q6 is connected to the node FB2 through a resistor, R9.

When the output voltage at Vout+, VOUT+, is in the range between Vbe(Q4) and (Vcc−Vbe(Q3)), transistors, Q3 and Q4, are activated; while transistors, Q1 and Q2, are deactivated. The noise reduction network does not provide feedback signals to the node FB1. When VOUT+ is less than Vbe(Q4), the transistor, Q4, becomes deactivated; while the transistor, Q2, becomes activated. The network provides an adjustable feedback current through Q2 to the node FB1. When VOUT+ is larger than (Vcc−Vbe(Q3)), the transistor, Q3, becomes, deactivated; while the transistor, Q1, becomes activated. The network provides an adjustable feedback current through Q1 to the node FB1. The same analysis applies to the node Vout− and the node FB2 in circuit of FIG. 5(c). When the output voltage at Vout−, VOUT−, is in the range between Vbe(Q8) and (Vcc−Vbe(Q7)), transistors, Q7 and Q8, are activated; while transistors, Q5 and Q6, are deactivated. The noise reduction network does not provide feedback signal to the node FB2. When VOUT− is less than Vbe(Q8), the transistor, Q8, becomes deactivated; while the transistor, Q6, becomes activated. The network provides an adjustable feedback current through Q6 to the node FB2. When VOUT− is larger than (Vcc−Vbe(Q7)), the transistor, Q7, becomes deactivated; while the transistor, Q5, becomes activated. The network provides an adjustable feedback current through Q5 to the node FB2.

Assume Vbe(Q3)=Vbe(Q4)=Vbe(Q7)=Vbe(Q8)=Vbe, the noise reduction network in FIGS. 5(b) and 5(c) produces an adjustable feedback current through the node FB1 when VOUT+ in the range [0, Vbe] and [Vcc−Vbe, Vcc]; and an adjustable feedback current through the node FB2 when VOUT− in the range [0, Vbe] and [Vcc−Vbe, Vcc]. These feedback currents define a minimum switching frequency of the amplifier control stage in FIG. 4. The increased minimum frequency produces a more “curved” sinusoidal waveform in the near “clipping” range of output signals, which is schematically shown in FIG. 5(d).

In present invention, a noise reduction feedback network is introduced between an amplifier control stage and an output stage. The noise reduction feedback network couples with the input terminals of the amplifier control stage with output terminals of the output stage. It monitors the output voltages of the output stage, and remains “inactivated” as long as output voltages are not near saturation. The waveforms of output voltage are the amplified curves of input voltages with substantially the same shape. Once output voltages are near saturation, the noise reduction feedback network starts to be activated. In one embodiment, it sends an adjustable current to the input terminals of amplifier control stage. The adjustable current increases and defines the minimum switching frequency of the amplifier control stage. As a result, the waveforms of output voltage near saturation become more “curved” sinusoidal waveforms comparing with those of input signal. In another embodiment, the noise reduction feedback network reduces the close-loop gain of the amplifier control stage. It has the similar effect on the output voltage near saturation and the waveforms of output voltage near saturation become more “curved” sinusoidal waveforms comparing with those of input signal. The present invention has many advantages over approaches in references. The circuit is very simple and has high efficiency and fast loop response. The output signals in non-saturation region, together with its quality, are not affected by the “inactivated” noise reduction feedback network. The output signals near saturation and inside saturation regions are amplified by less close-loop gains than those in non-saturation regions. Their waveforms become more “curved”, which, in turn, greatly reduce or eliminate audio noises near or in the saturation regions.

The description of the invention and its applications as set forth herein is illustrative and is not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and practical alternatives to and equivalents of the various elements of the embodiments are known to those of ordinary skill in the art. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims

1. A method, comprising:

providing an input signal;

deriving a first signal from said input signal, and providing said first signal to an output stage through an amplifier control stage;

using said first signal to drive said output stage to generate an ouput signal; and

deriving a noise reduction signal from said output signal, and providing said noise reduction signal to said amplifier control stage through a noise reduction feedback network.

2. The method in claim 1, wherein said input signal is an analog audio signal.

3. The method in claim 1, further comprising:

using said noise reduction signal to modulate the minimum switching frequency of said amplifier control stage.

4. The method in claim 1, further comprising:

using said noise reduction signal to modulate the closed loop gain of said amplifier control stage.

5. The method in claim 1, further comprising:

using said noise reduction signal to modulate the minimum switching frequency and the closed loop gain of said amplifier control stage.

6. A method, comprising:

providing an input signal;

deriving a first signal from said input signal, and providing said first signal to an output stage through an amplifier control stage;

using said first signal to drive an output stage to generate a second signal;

filtering the second signal to obtain an output signal; and

deriving a noise reduction signal from said output signal, and providing said noise reduction signal to said amplifier control stage through a noise reduction feedback network.

7. The method in claim 6, wherein said input signal is an analog audio signal.

8. The method in claim 6, further comprising:

using said noise reduction signal to modulate the minimum switching frequency of said, amplifier control stage.

9. The method in claim 6, further comprising:

using said noise reduction signal to modulate the close loop gain of said amplifier control stage.

10. The method in claim 6, further comprising:

using said noise reduction signal to modulate the minimum switching frequency and the closed loop gain of said amplifier control stage.

11. An apparatus, comprising:

an amplifier control stage to receive an input audio signal and generate a first signal;

an output stage coupled to said amplifier control stage and responsive to the first signal to generate an output signal; and

a noise reduction network to receive said output signal and generate a noise reduction signal to said control stage, said noise reduction network being capable of monitoring said ouput signal, detecting said output signal near saturation conditions, and modulating said control stage to remove audible oscillations near saturations.

12. The apparatus of claim 11, wherein said noise reduction network comprises:

a detect circuit to receive the output signal, and generate a control signal to a modulation circuit; and

the modulation circuit to receive said control signal from said detect circuit, to generate an adjustable signal or multiple adjustable signals to said amplifier control stage, and modulate said amplifier control stage to remove audible oscillations near output saturations.

13. The apparatus of claim 12, wherein said detect circuit comprises:

two back-to-back transistors to monitor said output signal, detect said output signal near saturation condition, be activated when said output signal is above a preset value, and provide a control signal or multiple control signals to said modulation circuit when said two back-to-back transistors are activated.

14. The apparatus of claim 12, wherein said detect circuit comprises:

two back-to-back “Zener” diodes to monitor said output signal, detect said output signal near saturation condition, be activated when said output signal is above a preset value, and provide a control signal or multiple control signals to said modulation circuit when said two back-to-back “Zener” diodes are activated.

15. The apparatus of claim 13 or 14, wherein said modulation circuit comprises a modulation transistor to receive said control signal from said detect circuit, and generate a modulation signal to modulate said control stage.

16. The apparatus of claim 15 wherein said modulation transistor is one of a set of multiple modulation transistors and said modulation signal is one of a set of multiple modulation signals.

17. The apparatus of claim 12, wherein said detect circuit comprises:

a detect transistor to monitor said output signal, detect said output signal near saturation condition, and be activated unless said output signal is close to the positive supply voltage within a preset value; and

a second detect transistor to monitor said output signal, detect said output signal near saturation condition, and be activated unless said output signal is close to the negative supply voltage or ground voltage within a preset value.

18. The apparatus of claim 17, wherein said first detect transistor is one of a set of multiple detect transistors; and the second detect transistor is one of a second set of multiple detect transistors.

19. The apparatus of claim 17, wherein said modulation circuit comprises:

a modulation transistor coupled to said first detect transistor to receive, and response to said control signal, wherein said modulation transistor is activated when the first detect transistor is deactivated, and is deactivated when the first detect transistor is activated; and

a second modulation transistor couple to said second detect transistor to receive, and response to said control signal, wherein said modulation transistor is activated when said second detect transistor is deactivated, and is deactivated when said second detect transistor is activated.

20. The apparatus of claim 19, wherein said first modulation transistor is one of a first set of modulation transistors; and said second modulation transistor is one of a second set of modulation transistors.

21. A method, comprising:

providing an analog audio input signal;

deriving a first signal from said input signal to a bang-bang controller through an amplifier control stage;

using said bang-bang controller to trigger generation of a second signal from said first signal;

providing said second signal to an output stage;

using said second signal to drive said output stage to generate an output signal;

deriving a noise reduction signal from said output signal by a noise reduction network; and

coupling said noise reduction signal to said bang-bang controller to remove audible oscillations near output saturations;

wherein said output signal generated by said output stage that is an amplified output signal substantially representative of said input signal.

22. The method of claim 21, wherein said noise reduction network detecting said output signal near saturation by comparing it with the activation voltage of two back-to-back transistors.

23. The method of claim 21, wherein said noise reduction network detecting said output signal near saturation by comparing it with the activation voltage of two back-to-back “Zener” diodes.

24. The method of claim 21, wherein said noise reduction network detecting said output signal near saturation by comparing it with the positive supply voltage of the amplifier through a transistor.

25. The method of claim 21, wherein said noise reduction network detecting said output signal near saturation by comparing it with the negative supply voltage or ground voltage through a transistor.