Patents by Inventor Wei Chen

Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395450
    Abstract: A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Jing-Ye Juang, Hsien-Wei Chen, Chia-Ling Lu, Shin-Puu Jeng
  • Publication number: 20230396557
    Abstract: Example methods and systems for policy-aware traffic forwarding for multiple types of network traffic are described. In one example, a computer system may extract identification information associated with a first client, wherein the first client is associated with a first type of network traffic and obtain a first policy associated with the first client. In response to detecting first network traffic of the first type from the first client, the computer system may (a) interwork the first network traffic into a data plane entity associated with the second type of network traffic, and (b) forward the first network traffic via the data plane entity according to the first policy. In response to detecting second network traffic of the second type from a second client, the computer system may forward the second network traffic via the data plane entity according to a second policy associated with the second client.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 7, 2023
    Applicant: Atayalan, Inc.
    Inventors: Rajesh PAZHYANNUR, Chih Hsin LIN, Yan Wei CHEN, Li Fung CHANG
  • Publication number: 20230395899
    Abstract: A heating method traction battery. The traction battery is connected to a switch circuit of a motor and configured to supply power to the motor via the switch circuit. The switch circuit includes multiple legs and the multiple legs are connected to the traction battery in parallel. The method includes: receiving a heating signal sent by a battery management system of the traction battery; and controlling, according to the heating signal, at least one of the multiple legs to form a short-circuit loop of the traction battery, the short-circuit loop being configured to discharge the traction battery and heat the traction battery during the discharging process.
    Type: Application
    Filed: August 21, 2023
    Publication date: December 7, 2023
    Inventors: Xinwei CHEN, Zhimin DAN, Chengyong LIU, Wei ZHANG, Yu YAN, Xian HUANG
  • Publication number: 20230397440
    Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Hung-Ju Li, Kuo-Pin Chang, Yu-Wei Ting, Ching-En Chen, Kuo-Ching Huang
  • Publication number: 20230395530
    Abstract: A semiconductor structure includes a substrate having a seal ring region and a circuit region, a dielectric interlayer over the substrate, one or more dielectric layers disposed over the dielectric interlayer, a connection structure disposed in the one or more dielectric layers in the seal ring region, and a metal plug disposed below the connection structure and disposed at least partially in the dielectric interlayer in the seal ring region. The connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 7, 2023
    Inventor: Hsien-Wei Chen
  • Publication number: 20230396800
    Abstract: Disclosed are a point cloud encoding and decoding method and device based on a two-dimensional regularization plane projection. The encoding method includes: acquiring original point cloud data; performing two-dimensional regularization plane projection on the original point cloud data to obtain a two-dimensional projection plane structure; obtaining a plurality of pieces of two-dimensional image information according to the two-dimensional projection plane structure; and encoding the plurality of pieces of two-dimensional image information to obtain code stream information. According to the present disclosure, the strong correlation representation of a point cloud on the two-dimensional projection plane structure is obtained, so that the spatial correlation of the point cloud is better reflected, and the encoding efficiency of the point cloud is improved. Moreover, a placeholder information map is used for assisting in encoding the depth information map, so that the encoding efficiency is further improved.
    Type: Application
    Filed: February 7, 2022
    Publication date: December 7, 2023
    Applicant: Honor Device Co., Ltd.
    Inventors: Fuzheng YANG, Wei ZHANG, Youguang YU, Yuxin DU, Zexing SUN, Tian CHEN, Ke ZHANG
  • Publication number: 20230395435
    Abstract: A method includes providing a structure having a first stack of nanostructures spaced vertically one from another and a second stack of nanostructures spaced vertically one from another, forming a dielectric layer wrapping around each of the nanostructures in the first and second stacks, depositing an n-type work function layer on the dielectric layer and a p-type work function layer on the n-type work function layer and over the first and second stacks. The n-type work function layer wraps around each of the nanostructures in the first stack. The p-type work function layer wraps around each of the nanostructures in the second stack. The method also includes forming an electrode layer on the p-type work function layer and over the first and second stacks.
    Type: Application
    Filed: June 5, 2022
    Publication date: December 7, 2023
    Inventors: Chih-Wei Lee, Jo-Chun Hung, Wen-Hung Huang, Jian-Hao Chen, Kuo-Feng Yu
  • Publication number: 20230395479
    Abstract: A semiconductor structure includes an assembly including an interposer, at least one semiconductor die attached to the interposer including interposer bonding pads, and a die-side underfill material portion located between the interposer and the at least one semiconductor die, a packaging substrate including substrate bonding pads, an array of solder material portions bonded to the interposer bonding pads and the substrate bonding pads, a central underfill material portion laterally surrounding a first subset of the solder material portions, and at least one peripheral underfill material portion contacting corner regions of the interposer and a respective surface segment of the central underfill material portion and having a different material composition than the central underfill material portion.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Jing-Ye Juang, Chia-Kuei Hsu, Ming-Chih Yew, Hsien-Wei Chen, Shin-Puu Jeng
  • Publication number: 20230394309
    Abstract: A method for executing a multi-task deep learning model for learning trends in multivariate time series is presented. The method includes collecting multi-variate time series data from a plurality of sensors, jointly learning both local and global contextual features for predicting a trend of the multivariate time series by employing a tensorized long short-term memory (LSTM) with adaptive shared memory (TLASM) to learn historical dependency of historical trends, and employing a multi-task one-dimensional convolutional neural network (1dCNN) to extract salient features from local raw time series data to model a short-term dependency between local time series data and subsequent trends.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Applicant: NEC Laboratories America, Inc.
    Inventors: Wei Cheng, Haifeng Chen, Jingchao Ni, Dongkuan Xu, Wenchao Yu
  • Publication number: 20230396378
    Abstract: A user equipment (UE) communicates with transmission-reception points (TRPs). When the UE generates uplink control information (UCI), it determines a higher layer index (HLI) value to target the UCI to the appropriate TRP. (Possible values of the HLI are associated with the TRPs.) For UCI on Physical Uplink Control Channel (PUCCH), the HLI value may be determined: based on an HLI value configured for a control resource set (CORESET), or for particular Physical Uplink Control Channel (PUCCH) resources; based on UCI type or spatial relation data or an index related to PUCCH resources. For UCI on a configured-grant Physical Uplink Shared Channel (PUSCH), the HLI value may be based on higher layer signals or an indicator relating to channel sounding on spatial relation data. For UCI on MsgA PUSCH in a two-step random access procedure, the HLI value may be based on PUSCH resource unit or PUSCH opportunity.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Yushu Zhang, Dawei Zhang, Haijing Hu, Wei Zeng, Yang Tang, Haitong Sun, Yuchul Kim, Hong He, Chunhai Yao, Chunxuan Ye, Weidong Yang, Oghenekome Oteri, Jie Cui, Fangli Xu, Yuqin Chen
  • Publication number: 20230394049
    Abstract: Methods, apparatus, systems, and computer-readable media are provided for automatically augmenting message exchange threads based on a detected tone of messages exchanged between participants. In various implementations, a message contributed to a message exchange thread involving one or more message exchange clients by a participant may be determined. In various implementations, an idle chatter score associated with the message may be calculated. In various implementations, either a conversational response to the message or content responsive to a search query generated based on the message may be selectively incorporated into the message exchange thread based at least in part on the idle chatter score. In some implementations, a search query suitability score associated with the message may also be calculated.
    Type: Application
    Filed: August 21, 2023
    Publication date: December 7, 2023
    Inventors: David Kogan, Wangqing Yuan, Wei Chen, Bryan Horling, Michael Itz
  • Publication number: 20230395543
    Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.
    Type: Application
    Filed: January 10, 2023
    Publication date: December 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai TIAN, Hongwen LI, Liang CHEN, Wei JIANG
  • Publication number: 20230395486
    Abstract: A method of forming semiconductor device includes forming interconnect structure over substrate; forming first passivation layer over the interconnect structure, and metal-insulator-metal capacitor in the first passivation layer; forming first redistribution layer including first pads over the first passivation layer, and first vias extending into the first passivation layer; conformally forming second passivation layer over the first redistribution layer and first passivation layer, and patterning the second passivation layer to form via openings exposing the first pads; forming second redistribution layer including second pads over the second passivation layer, and second vias in the first via openings, wherein the first and second redistribution layers include aluminum-copper alloy and copper, respectively; forming dielectric layer over the second redistribution layer, and patterning the dielectric layer to form via openings exposing some second pads; and forming bumps over the dielectric layer and in the
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Tsung-Chieh HSIAO, Liang-Wei WANG, Dian-Hau CHEN
  • Publication number: 20230395521
    Abstract: An interposer for a semiconductor package and a method of fabricating an interposer including a peripheral metal pad surrounding an alignment mark. The alignment mark and the surrounding peripheral metal pad are formed on a first dielectric material layer of the interposer. A second dielectric material layer is located over the first dielectric material layer and at least partially over the peripheral metal pad structure and includes an recess extending around a periphery of the alignment mark. A third dielectric material layer is located over the second dielectric material layer and extends into the recess and contacts the alignment mark, the first dielectric material layer, and optionally a portion of the peripheral metal pad. The peripheral metal pad may enhance the adhesion between the first, second and third dielectric material layers near the alignment mark structure and thereby reduce the likelihood of crack formation.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Meng-Liang Lin, Shin-Puu Jeng
  • Publication number: 20230393056
    Abstract: A method includes identifying, by pre-set criteria, a first plurality of optical channels and a second plurality of optical channels using optical data generated from a plurality of optical filters of a tester tool. The method also includes determining, from the optical data, a first plurality of fluid types detected by each channel in the first plurality of optical channels using a bootstrap fluid identification technique and determining, from the optical data and the first plurality of fluid types, a second plurality of fluid types detected by each channel in the second plurality of optical channels using a guided fluid identification technique. Further, the method includes generating a spectral signature indicating fluid types for each channel within the tester tool based on the first plurality of fluid types and second plurality of fluid types.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Zhonghuan Chen, Bin Dai, Wei Zhang
  • Publication number: 20230395598
    Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Jo-Chun Hung, Chih-Wei Lee, Wen-Hung Huang, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Hsin-Han Tsai, Yin-Chuan Chuang, Yu-Ling Cheng, Yu-Xuan Wang, Tefu Yeh
  • Publication number: 20230393373
    Abstract: A photographing lens assembly includes eight lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof. The seventh lens element has an image-side surface being concave in a paraxial region thereof. The eighth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, and the image-side surface of the eighth lens element has at least one critical point in an off-axis region thereof.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Chen LIN, Yu-Tai TSENG, Wei-Yu CHEN
  • Publication number: 20230395517
    Abstract: A method includes joining a first wafer to a second wafer, forming a first through-via penetrating through the first wafer and further extending into the second wafer, and forming a redistribution line on the first wafer. The redistribution line and the first through-via electrically connect a first conductive feature in the first wafer to a second conductive feature in the second wafer. An electrical connector is formed over the first wafer.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Hsien-Wei Chen, Jie Chen, Shin-Puu Jeng
  • Publication number: 20230393416
    Abstract: The invention relates to a pair of eyeglasses. The eyeglasses include a frame, a lens, and a movable tenon-like piece. The frame is provided with a mounting slot which is defined by a front wall, a rear wall, and a top wall of the frame and having an opening facing downward. An upper edge of the lens is mounted into the mounting slot. The movable tenon-like piece is inserted through the rear wall and the upper edge of the lens. When the movable tenon-like piece is moved horizontally from an unlocked-and-released position to a locked-and-fixed position, the lens with the upper edge mounted in the mounting slot of the frame is fixed in that state. The assembly of the frame with the lens is completed.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Inventor: PEN WEI CHEN
  • Publication number: 20230394014
    Abstract: A method for retrieving data on a web page includes performing a simulated user operation on a target web page to generate a result web page, retrieving a source code of the result web page, creating a data table according to the source code, and performing a data cleaning operation with the data table to generate cleaned data and store the cleaned data in a database. Each temporary row of the data table is corresponding to a quotation plan.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 7, 2023
    Applicant: DUN-QIAN Intelligent Technology Co., Ltd.
    Inventors: Yen-Chu Chen, Ling-Jung Lin, Shao-Chen Liu, Hsuan-Wei Chen, Shuh-Shian Tsai